- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8967 > ICS1562BM-001 (IDT, Integrated Device Technology Inc)IC VIDEO CLK SYNTHESIZER 16-SOIC PDF資料下載
參數(shù)資料
| 型號： | ICS1562BM-001 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 標準包裝： | 48 |
| 類型： | 時鐘/頻率合成器，時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，TTL，晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 其它名稱： | 1562BM-001 |
External Feedback Operation
The ICS1562B-201 option also supports the inclusion of an
external counter as the feedback divider of the PLL. This mode
is useful in graphic systems that must be “genlocked” to
external video sources.
When the EXTFBEN bit is set to logic 1, the phase-frequency
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal applied
to the EXTFBK input if the FBKPOL bit is set to logic 0.
VRAM Shift Clock Generation
The ICS1562B-201 option supports VRAM shift clock gen-
eration and interruption. By programming the N2 counter to
divide by 1, the LD/N2 output becomes a duplicate of the
LOAD output. When the SCEN bit is set, the LD/N2 output
may be synchronously started and stopped via the blank pin.
When BLANK is high, the LD/N2 will be free-running and in
phase with LOAD. When BLANK is taken low, the LD/N2
output is stopped at a low level. See Figure 5 for a diagram of
the sequence. Note that this use of the BLANK pin precludes its
use for phase comparator disable (see Line-Locked Operation).
Power-On Initialization
The ICS1562B has an internal power-on reset circuit that
performs the following functions:
1)
Sets the multiplexer to pass the reference frequency
to the CLK+ and CLK- outputs.
2)
Selects the modulus of the N1 divider (for the
LOAD clock) to be four.
These functions should allow initialization of most graphics
systems that cannot immediately provide for register program-
ming upon system power-up.
Because the power-on reset circuit is on the VDD supply, and
because that supply is filtered, care must be taken to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microseconds after the VDD supply reaches 4 volts.
Programming Notes
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in normal situations (i.e,
pixel clock generation for hi-res displays), keep the refer-
ence divider modulus as short as possible (for a frequency
at the output of the reference divider in the few hundred
kHz to several MHz range). If you need to go to a lower
phase comparator reference frequency (usually required
for increased frequency accuracy), that is acceptable, but
jitter performance will suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as shown
on the following page:
VRAM Shift Clock Control
BLANK
LOAD
LD/N2
Figure 5
ICS1562B
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843256BGILFT | IC SYNTHESIZER W/BUFF 24-TSSOP |
| AD5726YRSZ-500RL7 | IC DAC 12BIT QUAD SERIAL 16SSOP |
| VI-262-MW-F4 | CONVERTER MOD DC/DC 15V 100W |
| VI-J4H-MZ-F2 | CONVERTER MOD DC/DC 52V 25W |
| VI-J4H-MZ-F1 | CONVERTER MOD DC/DC 52V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1562BM-001T | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS1562BM-201 | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1562BM-201-4 | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1562BM-201-4LF | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS1562BM-201-4LFT | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。