參數(shù)資料
型號: ICL7660A
廠商: Intersil Corporation
英文描述: CMOS Voltage Converters(CMOS電壓變換器)
中文描述: CMOS電壓轉(zhuǎn)換器(的CMOS電壓變換器)
文件頁數(shù): 7/11頁
文件大?。?/td> 275K
代理商: ICL7660A
7
FN3072.7
October 10, 2005
The voltage regulator portion of the ICL7660 and ICL7660A is
an integral part of the anti-latchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the “LV” pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met.
1. The driver circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The ICL7660 and ICL7660A approach these conditions for
negative voltage conversion if large values of C
1
and C
2
are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS.
The energy lost is defined by:
E =
1
/
2
C
1
(V
12
- V
22
)
where V
1
and V
2
are the voltages on C
1
during the pump and
transfer cycles. If the impedances of C
1
and C
2
are relatively
high at the pump frequency (refer to Figure 12) compared to
the value of R
L
, there will be a substantial difference in the
voltages V
1
and V
2
. Therefore it is not only desirable to make
C
2
as large as possible to eliminate output voltage ripple, but
also to employ a correspondingly large value for C
1
in order to
achieve maximum efficiency of operation.
Do’s And Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply
voltages greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7660 and ICL7660A
and the + terminal of C
2
must be connected to GROUND.
5. If the voltage supply driving the ICL7660 and ICL7660A
has a large source impedance (25
- 30
), then a 2.2
μ
F
capacitor from pin 8 to ground may be required to limit
rate of rise of input voltage to less than 2V/
μ
s.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions. A 1N914 or similar diode placed
in parallel with C
2
will prevent the device from latching up
under these conditions. (Anode pin 5, Cathode pin 3).
V
OUT
= -V
IN
C
2
V
IN
C
1
S
3
S
4
S
1
S
2
8
3
2
5
3
7
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
FIGURE 13A. CONFIGURATION
FIGURE 13B. THEVENIN EQUIVALENT
FIGURE 13. SIMPLE NEGATIVE CONVERTER
1
2
3
4
8
7
6
5
+
-
10
μ
F
ICL7660
ICL7660A
V
OUT
=
-
V+
V+
+
-
10
μ
F
V+
+
-
R
O
V
OUT
ICL7660, ICL7660A
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