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參數(shù)資料
| 型號： | ICL7112LMDL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 2.0 Gbps 4x4 Crosspoint Switch 38-TSSOP -40 to 85 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP40 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 758K |
| 代理商： | ICL7112LMDL |
6-8
By adding a three-state buffer and two control gates, the
End-of-Conversion (EOC) output can be used to control a
“Start and Poll” interface (Figure 6). In this mode, the A
0
and
CS lines connect the EOC output to the data bus along with
the most significant byte of data. After pulsing the WR line to
initiate a conversion, the microprocessor continually reads
the most significant byte until it detects a high level on the
EOC bit. The “Start and Poll” interface increases data
throughput compared with the “Start and Wait” method by
eliminating delays between the conversion termination and
the microprocessor read operation.
Other interface configurations can be used to increase data
throughput without monopolizing the microprocessor during
waiting or polling operations by using the EOC line as an
interrupt generator as shown in Figure 7. After the conver-
sion cycle is initiated, the microprocessor can continue to
execute routines that are independent of the A/D converter
until the converter’s output register actually holds valid data.
For fastest data throughput, the ICL7112 can be connected
directly to the data bus but controlled by way of a Direct
V
IN
V
REF
AGND
DGND
ICL7112
V
IN +
SOURCE -
V
REF -
SOURCE +
FIGURE 4. RECOMMENDED GROUNDING TECHNIQUE TO ELIMINATE GROUND LOOP ERRORS
ICL7112
A
0
CS
RD
BUS
OVR
D
8
- D
11
D
0
- D
7
WR
A
0
- A
N
CS
RD
μ
P
OVR
D
0
- D
7
WR
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
A
0
READ
LOW BYTE
READ
HIGH BYTE
START
CONVERSION
WAIT
RD
A
0
CS
WR
FIGURE 5. “START AND WAIT” OPERATION
ICL7112
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