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參數(shù)資料
| 型號： | ICL7112KMDL |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, High-Speed, CMOS uP-Compatible A/D Converter |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP40 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 758K |
| 代理商： | ICL7112KMDL |
6-5
Pin Descriptions
PIN NO.
NAME
DESCRIPTION
1
No connection.
2
AGND
f
FORCE input for analog ground.
3
CS
Chip Select enables reading and writing (active low).
4
RD
ReaD (active low).
5
A
0
Byte select (low = D
0
-D
7
, high = D
8
-D
11
, OVR).
6
BUS
Bus select (low = outputs enabled by A
0
, high = all outputs enabled together).
7
DGND
Digital GrouND return.
8
D
11
Bit 11 (most significant bit).
High Byte
9
D
10
Bit 10
10
D
9
Bit 9
11
D
8
Bit 8
12
D
7
Bit 7
13
D
6
Bit 6
14
D
5
Bit 5
Low Byte
15
D
4
Bit 4
16
D
3
Bit 3
17
D
2
Bit 2
18
D
1
Bit 1
19
D0
Bit 0 (least significant bit).
20
No connection.
21
No connection.
22
No connection.
23
No connection.
24
No connection.
25
EOC
End of conversion flag (low = busy, high = conversion complete).
26
OVR
OVerRange flag (valid at end of conversion when output code exceeds full-scale;
three-state output enabled with high byte).
27
V
+
Positive power supply input.
Used for programming only. Must tie to V
+
for normal operation.
Used for programming only. Must tie to V
+
for normal operation.
28
PROG
29
TEST
30
OSC1
Oscillator inverter input.
31
OSC2
Oscillator inverter output.
Must tie to V
+
for normal operation.
32
TEST
33
WR
WRite pulse input (low starts new conversion).
34
C
AZ
V
-
Auto-zero capacitor connection (Note).
35
Negative power supply input.
Used in test, tie to V
-
.
36
COMP
37
V
IN
SENSE line for input voltage.
38
V
REF
SENSE line for reference input.
39
AGND
s
SENSE line for analog ground.
40
No connection
NOTE: The voltage of CAZ is driven; NEVER connect directly to ground.
Output
Data
Bits
(High =True)
ICL7112
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