參數(shù)資料
型號： ICL7112KIDL
廠商： HARRIS SEMICONDUCTOR
元件分類： ADC
英文描述： 12-Bit, High-Speed, CMOS uP-Compatible A/D Converter
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP40
文件頁數(shù)： 3/14頁
文件大小： 758K
代理商： ICL7112KIDL
6-3
Absolute Maximum Ratings
Supply Voltage (V
+
to DGND) . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Supply Voltage (V
-
to DGND). . . . . . . . . . . . . . . . . . . +0.3V to -6.5V
V
REF
, V
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
25V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1V to -1V
V
REF
, V
IN
, AGND Current. . . . . . . . . . . . . . . . . . . . . . . . . . . .25mA
Digital I/O Pin Voltages. . . . . . . . . . . . . . . . . . . . . -0.3V to V+ +0.3V
PROG to DGND Voltage . . . . . . . . . . . . . . . . . . . . V
-
to (V+ +0.3V)
T
A
= 25
o
C
Thermal Information
Operating Conditions
ICL7112XCXX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70
ICL7112XIXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 to 70
ICL7112XMXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to 125
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . .
Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . . 500mW
Derate above 70
o
C at 10mW/
o
C
Maximum Junction Temperature (Ceramic Package) . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
θ
JA
(
o
C/W)
___
θ
JC
(
o
C/W)
___
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. All voltages with respect to DGND, unless otherwise noted.
3. Assumes all leads soldered or welded to printed circuit board.
Electrical Specifications
Test Conditions: V+ = +5V, V- = -5V, V
REF
= -10V, T
A
= 25
o
C, f
CLK
= 500kHz, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST
CONDITIONS
J
K
L
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
ACCURACY
Resolution
RES
12
Bits
Resolution with No
Missing Codes
RES
(NMC)
Notes 4, 5, 6
R
M
T
MIN
-T
MAX
11
10
-
-
12
11
-
-
12
12
-
-
Bits
Integral Linearity
Error
I
LE
Notes 4, 5
R
M
T
MIN
-T
MAX
-
-
±
0.024
±
0.030
±
0.10
±
0.12
-
-
±
0.012
±
0.020
±
0.08
±
0.10
-
-
±
0.012
±
0.020
±
0.08
±
0.10
%FSR
Unadjusted Full
Scale Error
FSE
Adjust-
able to
Zero
C
R
M
T
MIN
T
MAX
-
-
-
-
-
-
%FSR
I
R
M
T
MIN
-T
MAX
-
-
±
0.10
±
0.13
±
0.10
±
0.14
±
1
±
1.5
-
-
±
0.08
±
0.11
±
0.08
±
0.12
±
1
±
1.5
-
-
±
0.08
±
0.11
±
0.08
±
0.12
±
1
±
1.5
M
R
M
T
MIN
-T
MAX
-
-
-
-
-
-
Zero Error
ZE
Notes 4, 5
R
M
T
MIN
-T
MAX
-
-
-
-
-
-
ANALOG INPUT
Analog Input
Range
V
IN
0
-
10.3
0
-
10.3
0
-
10.3
V
Input Resistance
R
IN
T
C
(R
IN
)
Notes 5, 8
4
-
9
4
-
9
4
-
9
k
Temperature
Coefficient of R
IN
REFERENCE INPUT
T
MIN
-T
MAX
-
-300
-
-
-300
-
-
-300
-
ppm/
o
C
Analog Reference
V
REF
R
REF
-
-10.0
-
-
-10.0
-
-
-10.0
-
V
Reference
Resistance
-
5
-
-
5
-
-
5
-
k
POWER SUPPLY SENSITIVITY
Power Supply
Rejection Ration
PSRR
V
+
, V
-
= 4.5 -5.5V
RM
T
MIN
-T
MAX
-
±
0.5
±
1
±
2
-
±
0.5
±
1
±
2
-
±
0.5
±
1
±
2
LSB
LOGIC INPUT
Low State
Input Voltage
V
IL
T
MIN
-T
MAX
-
-
0.8
-
-
0.8
-
-
0.8
V
ICL7112
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