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參數(shù)資料
| 型號(hào)： | TP13054A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器） |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 361K |
| 代理商： | TP13054A |
TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C – SEPTEMBER 1992 – REVISED JULY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclock(M)
Frequency of master clock
MCLKX and
MCLKR
Depends on the device used and
BCLKX/CLKSEL
1.536
1.544
2.048
MHz
fclock(B)
tw1
tw2
Frequency of bit clock, transmit
BCLKX
64
2048
kHz
Pulse duration, MCLKX and MCLKR high
160
ns
Pulse duration, MCLKX and MCLKR low
160
ns
tr1
Rise time of master clock
MCLKX and
MCLKR
MCLKX and
MCLKR
BCLKX
Measured from 20% to 80%
50
ns
tf1
Fall time of master clock
50
ns
tr2
tf2
Rise time of bit clock, transmit
Measured from 20% to 80%
50
ns
Fall time of bit clock, transmit
BCLKX
50
ns
tsu1
Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKX
↓
Pulse duration, BCLKX and BCLKR high
First bit clock after the leading
edge of FSX
100
ns
tw3
tw4
VIH = 2.2 V
VIL = 0.6 V
160
ns
Pulse duration, BCLKX and BCLKR low
160
ns
th1
Hold time, frame sync low after bit clock low
(long frame only)
Hold time, BCLKX high after frame sync
↑
(short frame only)
Setup time, frame sync high before bit clock
↓
(long frame only)
0
ns
th2
0
ns
tsu2
80
ns
td1
td2
Delay time, BCLKX high to data valid
Load = 150 pF plus 2 LSTTL loads
Load = 150 pF plus 2 LSTTL loads
0
140
ns
Delay time, BCLKX high to TSX low
140
ns
td3
Delay time, BCLKX (or 8 clock FSX in long frame only)
low to data output disabled
50
165
ns
td4
Delay time, FSX or BCLKX high to data valid (long
frame only)
Setup time, DR valid before BCLKR
↓
Hold time, DR valid after BCLKR or BCLKX
↓
Setup time, FSR or FSX high before BCLKR or
BCLKR
↓
CL = 0 pF to 150 pF
20
165
ns
tsu3
th3
50
ns
50
ns
tsu4
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
50
ns
th4
Hold time, FSX or FSR high after BCLKX or BCLKR
↓
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
100
ns
th5
Hold time, frame sync high after bit clock
↓
Long-frame sync pulse
(from 3 to 8 bit clock periods long)
100
ns
tw5
All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25
°
C.
Nominal input value for an LSTTL load is 18 k
.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
Minimum pulse duration of the frame sync pulse
(low level)
64 kbps operating mode
160
ns
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| TP13067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13067ADW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3067AN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13054ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP13054AN | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
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