參數(shù)資料
型號(hào): 79RC32K438300BBI
廠商: Integrated Device Technology, Inc.
英文描述: IDTTM InterpriseTM Integrated Communications Processor
中文描述: IDTTM InterpriseTM集成通信處理器
文件頁數(shù): 30/59頁
文件大?。?/td> 644K
代理商: 79RC32K438300BBI
30 of 59
May 25, 2004
IDT 79RC32438
Figure 13 PCI AC Timing Waveform
Figure 14 PCI AC Timing Waveform — PCI Reset in Host Mode
Figure 15 PCI AC Timing Waveform — PCI Reset in Satellite Mode
Tdo_10c
Tzd_10b
Tdz_10b
Tdo_10b
Thld_10c
Tsu_10c
Thld_10b
Tsu_10b
Thigh_10a
Tper_10a
valid
valid
PCICLK
Bussed output
Point to point output
Bussed input
Point to point input
Tlow_10a
Tpw_10d
PCI interface enabled
cold reset
warm reset
COLDRSTN
PCIRSTN (output)
RSTN
Note: During and after cold reset, PCIRSTN is tri-stated and requires a pull-down to reach a low state.
After the PCI interface is enabled in host mode, PCIRSTN will be driven either high or low depending on the
reset state of the 79RC32438.
(tri-state)
Tdz_10e
Tpw_10e
warm reset
CLKP
PCIRSTN (input)
RSTN
MDATA[15:0]
PCI bus signals
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