參數(shù)資料
型號(hào): IBMN364404CT3C-360
英文描述: x4 SDRAM
中文描述: x4內(nèi)存
文件頁數(shù): 25/71頁
文件大?。?/td> 1251K
代理商: IBMN364404CT3C-360
IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 25 of 71
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the
Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read
operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
COMMAND
READ Ax
0
NOP
NOP
NOP
NOP
NOP
*
NOP
NOP
t
CK2,
DQs
CAS latency = 2
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
Precharge A
t
CK3,
DQs
CAS latency = 3
DOUT Ax
0
DOUT Ax
1
DOUT Ax
2
DOUT Ax
3
t
RP
t
RP
*
Bank A can be reactivated at completion of t
RP
.
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*
(Burst Length = 8, CAS Latency = 2, 3)
相關(guān)PDF資料
PDF描述
IBMN364404CT3C-75A x4 SDRAM
IBMN364804CT3C-260 x8 SDRAM
IBMN364804CT3C-360 x8 SDRAM
IBMN364804CT3C-75A x8 SDRAM
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