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參數(shù)資料
| 型號： | HYS72T64300HP-3.7-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 20/50頁 |
| 文件大?。?/td> | 1423K |
| 代理商： | HYS72T64300HP-3.7-A |
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Internet Data Sheet
Rev. 1.22, 2007-06
07042006-834B-Z31V
21
HYS72T[64/128]3x0HP–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
t
LZ.DQS
t
MOD
t
MRD
t
OIT
t
QH
t
QHS
t
REFI
t
AC.MIN
0
2
0
t
HP
–
t
QHS
—
—
—
105
t
AC.MAX
12
—
12
—
340
7.8
3.9
—
ps
ns
nCK
ns
ps
ps
μ
s
μ
s
ns
9)22)
35)
35)
26)
27)
28)29)
29)30)
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
8) New units, ‘
t
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
t
‘ represents the actual
t
of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
t
CK
‘ is used for both concepts. Example:
t
XP
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
t
RFC
31)
t
RP
t
RP
t
RPRE
t
RPST
t
RTP
t
WPRE
t
WPST
t
WR
t
WTR
t
XARD
t
XARDS
t
RP
t
RP
+ 1
×
t
CK
0.9
0.4
7.5
0.35
0.4
15
7.5
2
7 – AL
—
—
1.1
0.6
—
—
0.6
—
—
—
—
ns
ns
t
CK.AVG
t
CK.AVG
ns
t
CK.AVG
t
CK.AVG
ns
ns
nCK
nCK
32)33)
32)34)
35)
35)
35)36)
t
XP
2
—
nCK
t
XSNR
t
XSRD
WL
t
RFC
+10
200
RL–1
—
—
ns
nCK
nCK
35)
Parameter
Symbol
DDR2–667
Unit
Notes
1)2)3)4)5)6)
7)8)
Min.
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64300HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64400HFA | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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