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參數(shù)資料
| 型號： | HYS72T64020HU-3-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Unbuffered DDR2 SDRAM Modules |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 35/73頁 |
| 文件大?。?/td> | 1574K |
| 代理商： | HYS72T64020HU-3-A |
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Internet Data Sheet
Rev. 1.41, 2006-11
03062006-0GN5-WTPW
35
HYS[64/72]T[16/32/64]0xxHU–[2.5/../5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 23
Definitions for
I
DD
Distributed Refresh Current
t
CK
=
t
CK.MIN.
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE
≤
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°
C max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2)
I
DD
specifications are tested after the device is properly initialized and
I
DD
parameter are specified with ODT disabled.
3) Definitions for
I
DD
see
Table 23
.
4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
I
DD2P
.
5) For details and notes see the relevant Qimonda component data sheet.
6)
I
,
I
and
I
current measurements are defined with the outputs disabled (
I
= 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
I
DD5D
I
DD6
I
DD7
6)
Parameter
Description
LOW
STABLE
FLOATING
SWITCHING
V
IN
≤
V
IL(ac).MAX
, HIGH is defined as
V
IN
≥
V
IH(ac).MIN
Inputs are stable at a HIGH or LOW level
Inputs are
V
REF
=
V
DDQ
/2
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Parameter
Symbol Note
1)2)3)4)5)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T64020HU-3S-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T512020HR | 240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512020HR-3.7-A | 240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512020HR-5-A | 240-Pin Registered-DDR2-SDRAM Modules |
| HYS72T512022EP | 240-Pin Dual Die Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64020HU-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64300HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64300HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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