參數(shù)資料
型號： HYS72T64020HR-3.7-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： GREEN, DIMM-240
文件頁數(shù)： 21/67頁
文件大?。?/td> 1462K
代理商： HYS72T64020HR-3.7-A
Internet Data Sheet
Rev. 1.21, 2007-03
09152006-J5FK-C565
21
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
8) New units, ‘
t
CK.AVG
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
t
CK.AVG
‘ represents the actual
t
CK.AVG
of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
t
‘ is used for both concepts. Example:
t
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
ERR(6-10PER).MIN
= – 272
ps and
t
ERR(6- 10PER).MAX
= + 293 ps, then
t
DQSCK.MIN(DERATED)
=
t
DQSCK.MIN
–
t
ERR(6-10PER).MAX
= – 400 ps – 293 ps = – 693 ps and
t
–
t
t
for DDR2–667 derates to
t
LZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and
t
LZ.DQ.MAX(DERATED)
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) Input waveform timing
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
V
level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
V
IL.AC
level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
V
il(DC)MAX
and
V
ih(DC)MIN
. See
Figure 2
.
13) If
t
DS
or
t
DH
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing
t
DH
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the
V
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the
V
IL.DC
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
V
IL.DC.MAX
and
V
IH.DC.MIN
Figure 2
.
16)
t
and
t
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (
t
HZ
), or begins driving (
t
LZ
) .
17)
t
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18)
t
is the minimum of the absolute half period of the actual input clock.
t
is an input parameter but not an input specification parameter.
It is used in conjunction with t
QHS
to derive the DRAM output timing
t
QH
. The value to be used for
t
QH
calculation is determined by the
following equation;
t
= MIN (
,
t
), where,
t
CH.ABS
is the minimum of the actual instantaneous clock high time;
t
CL.ABS
is the
minimum of the actual instantaneous clock low time.
19)
t
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
t
at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20)
t
QH
=
t
HP
–
t
QHS
, where:
t
HP
is the minimum of the absolute half period of the actual input clock; and
t
QHS
is the specification value under
the max column. {The less half-pulse width distortion present, the larger the
t
value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides
t
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 975 ps minimum. 2) If the system
provides
t
HP
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e.
t
JIT.PER
,
t
JIT.CC
, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the
V
IH.AC
level for a rising signal and
V
IL.AC
for a falling signal applied
to the device under test. See
Figure 3
.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
t
,
t
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the
V
IL.DC
level for a rising signal and
V
IH.DC
for a falling signal applied
to the device under test. See
Figure 3
.
25)
t
RPST
end point and
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
RPST
), or begins driving (
t
RPRE
).
Figure 1
shows a method to calculate these points when the device is no longer driving (
t
RPST
), or begins
driving (
t
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
RPRE.MIN(DERATED)
=
t
RPRE.MIN
+
t
JIT.PER.MIN
= 0.9 x
t
CK.AVG
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
= 1.1 x
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
相關(guān)PDF資料
PDF描述
HYS72T64020HR-3-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HU 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T32000HU-2.5-A 240-Pin Unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T64020HR-3-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HU 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T64020HU-2.5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
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