參數(shù)資料
型號(hào)： HYS72T64020HR-2.5-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 64M X 72 DDR DRAM MODULE, 0.4 ns, DMA240
封裝： GREEN, DIMM-240
文件頁(yè)數(shù)： 20/67頁(yè)
文件大?。?/td> 1462K
代理商： HYS72T64020HR-2.5-A
Internet Data Sheet
Rev. 1.21, 2007-03
09152006-J5FK-C565
20
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Four Activate Window for 1KB page size products
t
FAW
Four Activate Window for 2KB page size products
t
FAW
CAS to CAS command delay
Write recovery time
Auto-Precharge write recovery + precharge time
Internal write to read command delay
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
CKE minimum pulse width ( high and low pulse
width)
ODT turn-on delay
ODT turn-on
ODT turn-on (Power down mode)
35
45
2
15
WR +
t
nRP
7.5
7.5
t
RFC
+10
200
2
—
—
—
—
—
—
—
—
—
—
ns
ns
nCK
ns
nCK
ns
ns
ns
nCK
nCK
28)
28)
t
CCD
t
WR
t
DAL
t
WTR
t
RTP
t
XSNR
t
XSRD
t
XP
—
28)
29)30)
28)31)
28)
28)
—
—
t
XARD
t
XARDS
2
8 – AL
—
—
nCK
nCK
—
—
t
CKE
3
—
nCK
32)
t
AOND
t
AON
t
AONPD
2
t
AC.MIN
t
AC.MIN
+ 2
2
t
AC.MAX
+ 0.7
2 x
t
CK.AVG
+
t
AC.MAX
+ 1
2.5
t
AC.MAX
+ 0.6
2.5 x
t
CK.AVG
+
t
AC.MAX
+ 1
––
nCK
ns
ns
—
9)33)
—
ODT turn-off delay
ODT turn-off
ODT turn-off (Power down mode)
t
AOFD
t
AOF
t
AOFPD
2.5
t
AC.MIN
t
AC.MIN
+ 2
nCK
ns
ns
—
34)35)
—
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V. See notes
5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
t
ANPD
t
AXPD
t
MRD
t
MOD
t
OIT
t
DELAY
3
8
2
0
0
t
LS
+
t
CK .AVG
+
t
LH
nCK
nCK
nCK
ns
ns
ns
—
—
—
—
12
12
––
28)
28)
—
Parameter
Symbol
DDR2–800
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
相關(guān)PDF資料
PDF描述
HYS72T64020HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HU 240-Pin Unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T64020HR-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HU 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*