參數(shù)資料
型號(hào)： HYS72T64001HR-3S-A
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： GREEN, DIMM-240
文件頁數(shù)： 18/67頁
文件大小： 1462K
代理商： HYS72T64001HR-3S-A
Internet Data Sheet
Rev. 1.21, 2007-03
09152006-J5FK-C565
18
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 14
Speed Grade Definition Speed Bins for DDR2–667
TABLE 15
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–667C
DDR2–667D
Unit
Note
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3
3
45
57
12
12
8
8
8
70000
—
—
—
5
3.75
3
45
60
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Speed Grade
DDR2–533C
DDR2–400B
Unit
Note
QAG
Sort Name
–3.7
–5
CAS-RCD-RP latencies
4–4–4
3–3–3
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
5
5
5
40
55
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
相關(guān)PDF資料
PDF描述
HYS72T64001HR-5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-2.5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T64020HR-3-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T64001HR-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T64020GR 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules
HYS72T64020GR-37-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules
HYS72T64020GR-3-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules
HYS72T64020GR-5-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered DIMM Modules
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