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| 型號： | HYS72T64000HU-2.5-B |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin unbuffered DDR2 SDRAM Modules |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.4 ns, DMA240 |
| 封裝： | GREEN, UDIMM-240 |
| 文件頁數(shù)： | 23/87頁 |
| 文件大小： | 1723K |
| 代理商： | HYS72T64000HU-2.5-B |
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Internet Data Sheet
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
23
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2–667
26)
t
QH
=
t
HP
–
t
QHS
, where:
t
HP
is the minimum of the absolute half period of the actual input clock; and
t
QHS
is the specification value under the
max column. {The less half-pulse width distortion present, the larger the
t
value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides
t
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 975 ps minimum. 2) If the system
provides
t
HP
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 1080 ps minimum.
27)
t
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
t
at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28)
t
RPST
end point and
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
), or begins driving (
t
).
Figure 3
shows a method to calculate these points when the device is no longer driving (
t
), or begins
driving (
t
RPRE
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
=
t
+
t
= 0.9 x
t
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
=
t
+
t
= 0.4 x
t
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
t
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP
= 15 ns, the device will support
t
= RU{
t
/
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)8)
Min.
Max.
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
DQS latching rising transition to associated clock
edges
t
AC
t
CCD
t
CH.AVG
t
CK.AVG
t
CKE
–450
2
0.48
3000
3
+450
—
0.52
8000
—
ps
nCK
t
CK.AVG
ps
nCK
9)
10)11)
12)
t
CL.AVG
t
DAL
t
DELAY
0.48
WR +
t
nRP
t
IS
+
t
CK .AVG
+
t
IH
175
0.35
–400
0.35
0.35
—
– 0.25
0.52
—
—
t
CK.AVG
nCK
ns
10)11)
13)14)
t
DH.BASE
t
DIPW
t
DQSCK
t
DQSH
t
DQSL
—
—
+400
—
—
240
+ 0.25
ps
t
CK.AVG
ps
t
CK.AVG
t
CK.AVG
ps
t
CK.AVG
19)20)15)
9)
16)
t
DQSS
17)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T64000HU-25F-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3.7-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3S-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-5-B | 240-Pin unbuffered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64000HU-25F-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3.7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-37-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T64000HU-3-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
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