參數(shù)資料
型號: HYS72T64000HF
廠商: QIMONDA
英文描述: 240-Pin Fully-Buffered DDR2 SDRAM Modules
中文描述: 240針全緩沖DDR2內(nèi)存模組
文件頁數(shù): 20/42頁
文件大?。?/td> 1052K
代理商: HYS72T64000HF
Internet Data Sheet
Rev. 1.2, 2006-11
03292006-GUME-ERC3
20
HYS72T[64/128/256]4[00/20]HFD–[3S/3.7]–A
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27
termination for command, address, and clocks, and 47
termination for control.
7. Termination is referenced to V
TT
= V
DD
/ 2.
MemBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
Electrical Idle
DRAM Idle (0 BW)
Primary channel Disabled
Secondary channel Disabled
CKE low. Command and Address lines Floated
DRAM clock active, ODT and CKE driven low
I
CC_MEMBIST
I
DD_MEMBIST
I
CC_EI
I
DD_EI
Parameter
Symbol
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