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參數(shù)資料
| 型號： | HYS72T512422HFN |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Fully-Buffered DDR2 SDRAM Modules |
| 中文描述： | 240針全緩沖DDR2內(nèi)存模組 |
| 文件頁數(shù)： | 15/41頁 |
| 文件大小： | 985K |
| 代理商： | HYS72T512422HFN |
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Internet Data Sheet
Rev. 1.3, 2006-12
03292006-QQ89-IKE4
15
HYS72T512[4/5]22HFN–[3S/3.7]–A
240-Pin Fully-Buffered DDR2 SDRAM Modules
Hardware aligns the read data and check-bits to a single core
clock. The Advanced Memory Buffer provides four copies of
the command clock phase references (CLK[3:0]) and write
data/check-bit strobes (DQSs) for each DRAM nibble.
3.3.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface
to allow system access to configuration registers independent
of the FB-DIMM link. The Advanced Memory Buffer will never
be a master on the SMBus, only a slave. Serial SMBus data
transfer is supported at 100 kHz. SMBus access to the
Advanced Memory Buffer may be a requirement to boot and
to set link strength, frequency and other parameters needed
to insure robust configurations. It is also required for
diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by
the unique ID.
3.3.3
Channel Latency
FB-DIMM channel latency is measured from the time a read
request is driven on the FB-DIMM channel pins to the time
when the first 16 bytes (2nd chunk) of read completion data is
sampled by the memory controller. When not using the
Variable Read Latency capability, the latency for a specific
DIMM on a channel is always equal to the latency for any
other DIMM on that channel. However, the latency for each
DIMM in a specific configuration with some number of DIMMs
installed may not be equal to the latency for each FB-DIMM
in a configuration with some different number of DIMMs
installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the
channel. Because the channel is based on the point-to-point
interconnection of buffer components between DIMMs,
memory requests are required to travel through N-1 buffers
before reaching the Nth buffer. The result is that a 4 DIMM
channel configuration will have greater idle read latency
compared to a 1 DIMM channel configuration. The Variable
Read Latency capability can be used to reduce latency for
DIMMs closer to the host. The idle latencies listed in this
section are representative of what might be achieved in
typical AMB designs. Actual implementations with latencies
less than the values listed will have higher application
performance and vice versa.
3.3.4
Peak Theoretical Channel Throughput
An FB-DIMM channel transfers read completion data on the
Northbound data connection. 144 bits of data are transferred
for every Northbound data frame. This matches the 18-byte
data transfer of an ECC DDR DRAM in a single DRAM
command clock. A DRAM burst of 8 from a single channel or
a DRAM burst of four from two lock stepped channels
provides a total of 72 bytes of data (64 bytes plus 8 bytes
ECC). The FB-DIMM frame rate matches the DRAM
command clock because of the fixed 6:1 ratio of the FB-DIMM
channel clock to the DRAM command clock. Therefore, the
Northbound data connection will exhibit the same peak
theoretical throughput as a single DRAM channel. For
example, when using DDR2 533 DRAMs, the peak theoretical
bandwidth of the Northbound data connection is 4.267
GB/sec. Write data is transferred on the Southbound
command and data connection, via Command+Wdata
frames. 72 bits of data are transferred for every
Command+Wdata frame. Two Command+Wdata frames
match the 18-byte data transfer of an ECC DDR DRAM in a
single DRAM command clock. A DRAM burst of 8 transfers
from a single channel, or a burst of 4 from two lock-step
channels provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). When the frame rate matches the DRAM
command clock, the Southbound command and data
connection will exhibit one half the peak theoretical
throughput of a single DRAM channel. For example, when
using DDR2 533 DRAMs, the peak theoretical bandwidth of
the Southbound command and data connection is 2.133
GB/sec. The total peak theoretical throughput for a single FB-
DIMM channel is defined as the sum of the peak theoretical
throughput of the Northbound data connection and the
Southbound command and data connection. When the frame
rate matches the DRAM command clock, this is equal to 1.5
times the peak theoretical throughput of a single DRAM
channel. For example, when using DDR2 533 DRAMs, the
peak theoretical throughput of a single DDR2-533 channel
would be 4.267 GB/sec., while the peak theoretical
throughput of the entire FB-DIMM PC4200F channel would
be 6.4GB/sec.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T512422HFN-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T512422HFN-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T512522HFN-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T512522HFN-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T64000EU-2.5-B2 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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