參數(shù)資料
型號： HYS72T512420EFA
廠商： QIMONDA
英文描述： 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
中文描述： 240針全緩沖DDR2內(nèi)存模組DDR2 SDRAM的符合RoHS產(chǎn)品
文件頁數(shù)： 17/37頁
文件大小： 1270K
代理商： HYS72T512420EFA
HYS72T512420EFA–[25F/3S]–C
Fully-Buffered DDR2 SDRAM Modules
Internet Data Sheet
Rev.1.20, 2007-10-19
03202007-06NE-DYYI
17
TABLE 10
Supply Voltage Levels and DC Operating Conditions
TABLE 11
FB-DIMM Latency Range
3) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85
°
C case
temperature before initiating self-refresh operation.
4) Above 85
°
C DRAM case temperature the Auto-Refresh command has to be reduced to
t
REFI
= 3.9
μ
s.
Parameter
Symbol
Limit Values
Unit
Notes
Min.
Nom.
Max.
AMB Supply Voltage DC
AMB Supply Voltage DC + AC
DRAM Supply Voltage
Termination Voltage
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
V
CC
1.455
1.425
1.7
0.48
×
V
DD
3.0
2.1
—
1.0
—
–90
–5
1.5
1.5
1.8
0.50
×
V
DD
3.3
—
—
—
—
—
—
1.575
1.590
1.9
0.52
×
V
DD
3.6
V
DDSPD
0.8
—
+0.5
+90
+5
V
V
V
V
V
V
V
V
V
μΑ
μΑ
1)
1) At 0KHz - 30KHz
2) AT 30KHz - 1 MHz
3) Applies for SMB and SPD Bus Signals
4) Applies for AMB CMOS Signal RESET
5) For all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
2)
V
DD
V
TT
V
DDSPD
V
IH(DC)
V
IL(DC)
V
IH(DC)
V
IL(DC)
I
L
I
L
–
–
–
3)
3)
4)
3)
4)
5)
Parameter
DDR2–800D
DDR2–667D
Unit
Note
Min.
Nom.
Max.
Min.
Typ.
Max.
t
C2D_DIMM
t
RESAMPLE_DIMM_SB
t
RESAMPLE_DIMM_NB
t
RESYNC_DIMM_SB
t
RESYNC_DIMM_NB
Tbd
Tbd
Tbd
Tbd
Tbd
19.35
1.68
1.48
2.66
2.54
Tbd
Tbd
Tbd
Tbd
Tbd
17.5
1.4
1.3
2.5
2.4
21
1.69
1.73
2.8
2.8
21.5
2.4
2.3
3.7
3.6
ns
ns
ns
ns
ns
1)2)
1) For DDR-800D and DDR-800E no Jedec Standart values are avalible for Min. and Max parameter.
2) Measured delay at FBDIMM gold finger between the center of the1st UI of command frame on the primary southbound lane 81 (connector
pins 102 & 103) and the center of the 1st UI of return data on the primary northbound lane 0 (connector pins 22 & 23) – [CL (DRAM CAS
latency) value] * [frame clock period – AL (DRAM additional latency) value * frame clock period].
3) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8 (connector pins 102
& 103) and the center of the 1st UI of the same frame on the secondary southbound lane 8 (connector pins 222 & 223).
4) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
5) Measured delay at FBDIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 (connector pins
142 & 143) and the center of the 1st UI of the same frame on the primary northbound lane 0 (connector pins 22 & 23).
2)3)
2)4)
2)5)
2)6)
相關(guān)PDF資料
PDF描述
HYS72T512420EFA-25F-C 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
HYS72T512420EFA-3S-C 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
HYS72T512422HFN-3S-A 240-Pin Fully-Buffered DDR2 SDRAM Modules
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T512420EFA-25F-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
HYS72T512420EFA-3S-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products
HYS72T512422HFN 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T512422HFN-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T512422HFN-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
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