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參數(shù)資料
| 型號： | HYS72T32000HR |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 240針DDR2 SDRAM的注冊模塊 |
| 文件頁數(shù)： | 22/67頁 |
| 文件大?。?/td> | 1462K |
| 代理商： | HYS72T32000HR |
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Internet Data Sheet
Rev. 1.21, 2007-03
09152006-J5FK-C565
22
HYS72T[32/64]0xxHR–[2.5/3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.DUTY
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
=
t
+
t
= 0.4 x
t
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
RP
t
CK.AVG
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
= 15 ns, the device will support
t
= RU{
t
/
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{
t
(ns) /
t
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
t
, if the result
of the division is not already an integer, round up to the next highest integer.
t
CK
refers to the application clock period. Example: For
DDR2–533 at
t
CK
= 3.75 ns with
t
WR
programmed to 4 clocks.
t
DAL
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30)
t
DAL.nCK
= WR [nCK] +
t
nRP.nCK
= WR + RU{
t
RP
[ps] /
t
CK.AVG
[ps] }, where WR is the value programmed in the EMR.
31)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
32)
t
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
t
IS
+ 2 x
t
CK
+
t
IH
.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND
.
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–
t
–
t
} and {–
t
–
t
ERR(6-10PER).MIN
} of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has
t
= – 272 ps,
t
ERR(6- 10PER).MAX
= + 293 ps,
t
JIT.DUTY.MIN
= – 106 ps and
t
JIT.DUTY.MAX
= + 94 ps,
then
t
AOF.MIN(DERATED)
=
t
AOF.MIN
+ {–
t
–
t
t
AOF.MAX(DERATED)
=
t
AOF.MAX
+ {–
t
JIT.DUTY.MIN
ERR(6-10PER).MIN
} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
Parameter
Symbol
DDR2–667
Unit
Note
1)2)3)4)5)6)7)
8)
Min.
Max.
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
DQ and DM input setup time
DQ and DM input hold time
Control & address input pulse width for each input
t
IPW
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
CK half pulse width
t
AC
t
DQSCK
t
CH.AVG
t
CL.AVG
t
CK.AVG
t
DS.BASE
t
DH.BASE
–450
–400
0.48
0.48
3000
100
175
0.6
0.35
—
t
AC.MIN
2 x
t
AC.MIN
—
Min (
t
CH.ABS
,
t
CL.ABS
)
—
t
HP
–
t
QHS
RL–1
+450
+400
0.52
0.52
8000
—
—
—
—
t
AC.MAX
t
AC.MAX
t
AC.MAX
240
__
ps
ps
t
CK.AVG
t
CK.AVG
ps
ps
ps
t
CK.AVG
t
CK.AVG
ps
ps
ps
ps
ps
9)
9)
10)11)
10)11)
—
12)13)14)
13)14)15)
—
—
t
DIPW
t
HZ
t
LZ.DQS
t
LZ.DQ
9)16)
9)16)
9)16)
17)
t
HP
18)
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
t
QHS
t
QH
WL
340
—
ps
ps
nCK
19)
20)
—
相關(guān)PDF資料 |
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|---|---|
| HYS72T32000HR-2.5-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-5-A | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T32000HR-2.5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T32000HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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