參數(shù)資料
型號(hào)： HYS72T256322HP
廠商： QIMONDA
英文描述： 240-Pin Dual-Die Registered DDR2 SDRAM Modules
中文描述： 240針雙模具注冊DDR2 SDRAM的模塊
文件頁數(shù)： 25/36頁
文件大?。?/td> 1002K
代理商： HYS72T256322HP
Internet Data Sheet
Rev. 1.01, 2006-09
03062006-PK3L-ZYSE
26
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
This chapter contains the Specifications and Conditions.
TABLE 18
I
DD
Measurement Conditions
Note
1)2)3)4)5)6)7)8)
Parameter
Symbol
Operating Current 0
One bank Active - Precharge;
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
, CKE is HIGH, CS is
HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
,
t
RCD
=
t
RCD.MIN
, AL = 0, CL = CL
.MIN
; CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING
.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Distributed Refresh Current
t
CK
=
t
CK.MIN
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
I
DD0
I
DD1
I
DD2N
I
DD2P
I
DD2Q
I
DD3P(0)
I
DD3P(1)
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
相關(guān)PDF資料
PDF描述
HYS72T256322HP-3.7-A 240-Pin Dual-Die Registered DDR2 SDRAM Modules
HYS72T256322HP-3S-A 240-Pin Dual-Die Registered DDR2 SDRAM Modules
HYS72T32000HP 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T32000HR-2.5-A 240-Pin Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256322HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules
HYS72T256322HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules
HYS72T256420HFD-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T256420HFD-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
HYS72T256420HFD-3S-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules
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