參數(shù)資料
型號: HYS72T256220HR-3S-B
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Registered DDR2 SDRAM Modules
中文描述: 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝: GREEN, RDIMM-240
文件頁數(shù): 27/52頁
文件大?。?/td> 1250K
代理商: HYS72T256220HR-3S-B
Internet Data Sheet
Rev. 1.2, 2007-01
03292006-JXZQ-CG6T
27
HYS72T[64/128/256]xxxHR–[3S/3.7/5]–B
240-Pin Registered DDR2 SDRAM
3.4
I
DD
Specifications and Conditions
List of tables defining
I
DD
Specifications and Conditions.
Table 18 “IDD Measurement Conditions” on Page 27
Table 21 “IDD Specification for HYS72T[64/128/256]xxxHR–3.7–B” on Page 30
Table 22 “IDD Specification for HYS72T[64/128/256]xxxHR–5–B” on Page 31
TABLE 18
I
DD
Measurement Conditions
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
. Both are measured from
t
, which is interpreted differently per speed bin. For DDR2-400/533,
t
AOFD
is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK
= 5 ns.
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
One bank Active - Precharge;
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
,
t
RCD
=
t
RCD.MIN
, AL = 0, CL =
CL
MIN
; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL =
CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL =
CL
MIN
;
t
CK
=
t
CKMIN
;
t
RAS
=
t
RASMAX
;
t
RP
=
t
RPMIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT
= 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL =
CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
DD0
I
DD1
6)
I
DD2N
I
DD2P
I
DD2Q
I
DD3N
I
DD3P(0)
I
DD3P(1)
I
DD4R
6)
I
DD4W
相關(guān)PDF資料
PDF描述
HYS72T256220HR-5-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T64000HR-3.7-B 240-Pin Registered DDR2 SDRAM Modules
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HYS72T64000HR-5-B 240-Pin Registered DDR2 SDRAM Modules
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參數(shù)描述
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HYS72T256322HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules
HYS72T256322HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules