參數(shù)資料
型號(hào)： HYS72T256023HR-5-A
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 240-Pin Registered DDR2 SDRAM Modules
中文描述： 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 26/41頁(yè)
文件大?。?/td> 1063K
代理商： HYS72T256023HR-5-A
Internet Data Sheet
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
26
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 16
ODT AC Character. and Operating Conditions for DDR2-667
TABLE 17
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD
t
ANPD
t
AXPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
2
t
AC.MIN
t
AC.MIN
+ 2 ns
2.5
t
AC.MIN
t
AC.MIN
+ 2 ns
3
8
2
t
AC.MAX
+ 0.7 ns
2
t
CK +
t
AC.MAX
+ 1 ns
2.5
t
AC.MAX
+ 0.6 ns
2.5
t
CK +
t
AC.MAX
+ 1 ns
—
—
nCK
ns
ns
nCK
ns
ns
nCK
nCK
1)
1) New units, '
t
' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit '
t
' represents the actual
t
of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, '
t
CK
' is used for both concepts. Example:
t
XP
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 ×
t
CK.AVG
+
t
EPR.2PER(MIN)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
, which is interpreted differently per speed bin. For DDR2-667/800,
t
AOND
is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
. Both are measured from
t
AOFD
, which is interpreted differently per speed bin. For DDR2-667/800,if
t
CK.AVG
=
3 ns is assumed,
t
AOFD
= 1.5 ns (0.5
×
3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
1)2)
1)
1)
1)3)
1)
1)
1)
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD
t
ANPD
t
AXPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
2
t
AC.MIN
t
AC.MIN
+ 2 ns
2.5
t
AC.MIN
t
AC.MIN
+ 2 ns
3
8
2
t
AC.MAX
+ 1 ns
2
t
CK +
t
AC.MAX
+ 1 ns
2.5
t
AC.MAX
+ 0.6 ns
2.5
t
CK +
t
AC.MAX
+ 1 ns
—
—
t
CK
ns
ns
t
CK
ns
ns
t
CK
t
CK
1)
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
, which is interpreted differently per speed bin. For DDR2-400/533,
t
AOND
is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK
= 5 ns.
2)
相關(guān)PDF資料
PDF描述
HYS72T512022HR 240-Pin Registered DDR2 SDRAM Modules
HYS72T512022HR-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T512022HR-3S-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T512022HR-5-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T256322HP 240-Pin Dual-Die Registered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T256040HP 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256040HP-3.7-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256040HP-3S-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256040HR 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256040HR-3.7-A 制造商:QIMONDA 制造商全稱(chēng):QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
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