- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385436 > HYS72T256023 (QIMONDA) 240-Pin Registered DDR2 SDRAM Modules PDF資料下載
參數(shù)資料
| 型號： | HYS72T256023 |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 240針DDR2 SDRAM的注冊模塊 |
| 文件頁數(shù)： | 16/41頁 |
| 文件大?。?/td> | 1063K |
| 代理商： | HYS72T256023 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
Internet Data Sheet
Rev. 1.2, 2007-01
03292006-AYVF-ZIIJ
16
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (
t
CK
= 5ns with
t
RAS
= 40ns).
TABLE 12
Speed Grade Definition
Speed Grade
DDR2–667
DDR2–533C
DDR2–400B
Unit
Note
QAG Sort Name
–3S
–3.7
–5
CAS-RCD-RP latencies
5–5–5
4–4–4
3–3–3
t
CK
Parameter
Symbol
Min.
Max.
Min.
Max.
Min.
Max.
—
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
t
CK
t
CK
t
CK
t
RAS
t
RC
t
RCD
t
RP
5
3.75
3
45
60
15
15
8
8
8
70000
—
—
—
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
5
5
5
40
55
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
4) The output timing reference voltage level is
V
TT
.
5)
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
t
REFI
.
1)2)3)4)
1)2)3)4)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T256023HR | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256023HR-5-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512022HR | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512022HR-3.7-A | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T512022HR-3S-A | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256023HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256023HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。