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參數(shù)資料
| 型號： | HYS72T256020HU-3S-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Unbuffered DDR2 SDRAM Modules |
| 中文描述： | 256M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 28/61頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | HYS72T256020HU-3S-A |
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Internet Data Sheet
Rev. 1.32, 2006-09
03062006-5RK8-1X8J
28
HYS[64/72]T256xxxHU–[3/…/5]–A
Unbuffered DDR2 SDRAM Modules
13) The
t
HZ
,
t
RPST
and
t
LZ
,
t
RPRE
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
t
), or begins driving (
t
t
).
t
and
t
transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85
°
C
and 95
°
C.
15) 0 °C
≤
T
CASE
≤
85
°
C
16) 85
°
C
<
T
CASE
≤
95
°
C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
t
timing parameter depends on the page size of the DRAM organization. See
Table 4 “Ordering Information for RoHS
Compliant Products” on Page 5
.
19) The maximum limit for the
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the
t
timing parameter, where
WR
[cycles] =
t
(ns)/
t
(ns) rounded
up to the next integer value.
t
= WR + (
t
/
t
). For each of the terms, if not already an integer, round to the next highest integer.
t
CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum
t
WTR
is two clocks when operating the DDR2-SDRAM at frequencies
≤ 200 ΜΗ
z.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD
can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS
has to be satisfied.
相關PDF資料 |
PDF描述 |
|---|---|
| HYS72T256020HU-3.7-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T256020HU-3-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T256020HU-5-A | 240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T256023 | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256023HR | 240-Pin Registered DDR2 SDRAM Modules |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256020HU-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Unbuffered DDR2 SDRAM Modules |
| HYS72T256023 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256023HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256023HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T256040HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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