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參數(shù)資料
| 型號(hào)： | HYS72T256000HR |
| 廠商： | QIMONDA |
| 英文描述： | 240-Pin Registered DDR SDRAM Modules |
| 中文描述： | 240針DDR SDRAM內(nèi)存模塊注冊(cè) |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | HYS72T256000HR |
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Internet Data Sheet
Rev. 1.4, 2007-02
03062006-GD6J-14FP
28
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 18
Definitions for
I
DD
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
CK
=
t
CK.MIN.
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Self-Refresh Current
CKE
≤
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°
C max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2)
I
DD
specifications are tested after the device is properly initialized and
I
DD
parameter are specified with ODT disabled.
3) Definitions for
I
DD
see
Table 18
4)
I
,
I
and
I
current measurements are defined with the outputs disabled (
I
= 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
I
DD2P
6) For details and notes see the relevant Qimonda component data sheet
I
DD3N
I
DD3P(0)
I
DD3P(1)
I
DD4W
I
DD5B
I
DD5D
I
DD6
I
DD7
Parameter
Description
LOW
STABLE
FLOATING
SWITCHING
V
IN
≤
V
IL(ac).MAX
, HIGH is defined as
V
IN
≥
V
IH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are
V
REF
=
V
DDQ
/2
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Parameter
Symbol Note
1)2)3)4)5)6)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T256000HR-3.7-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-3S-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-5-A | 240-Pin Registered DDR SDRAM Modules |
| HYS72T128020EU-2.5-B2 | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020EU-25F-B2 | 240-Pin unbuffered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256000HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256000HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
| HYS72T256020EU-2.5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T256020EU-25F-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules |
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