參數(shù)資料
型號： HYS72T1G242EP-3-C
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 240-Pin Dual Die Registered DDR2 SDRAM Modules
中文描述： 1G X 72 DDR DRAM MODULE, 0.65 ns, DMA240
封裝： GREEN, RDIMM-240
文件頁數(shù)： 22/43頁
文件大?。?/td> 1309K
代理商： HYS72T1G242EP-3-C
Internet Data Sheet
Rev. 1.0, 2007-07
07242007-LR08-OZC0
22
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Control & address input pulse width for each input
t
IPW
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
0.6
200
2 x
t
AC.MIN
t
AC.MIN
0
2
0
t
HP
–
t
QHS
—
—
—
127.5
—
—
t
AC.MAX
t
AC.MAX
12
—
12
—
340
7.8
3.9
—
t
CK.AVG
ps
ps
ps
ns
nCK
ns
ps
ps
μ
s
μ
s
ns
t
IS.BASE
t
LZ.DQ
t
LZ.DQS
t
MOD
t
MRD
t
OIT
t
QH
t
QHS
t
REFI
24)25)
9)22)
9)22)
35)
35)
26)
27)
28)29)
29)30)
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until
V
REF
stabilizes. During the period before
V
REF
stabilizes, CKE = 0.2 x
V
DDQ
is recognized as low.
7) The output timing reference voltage level is
V
TT
.
t
RFC
31)
t
RP
t
RPRE
t
RPST
t
RRD
t
RP
+ 1
×
t
CK
0.9
0.4
7.5
—
1.1
0.6
—
ns
t
CK.AVG
t
CK.AVG
ns
32)33)
32)34)
35)
t
RRD
10
—
ns
35)
t
RTP
t
WPRE
t
WPST
t
WR
t
WTR
t
XARD
t
XARDS
7.5
0.35
0.4
15
7.5
2
7 – AL
—
—
0.6
—
—
—
—
ns
t
CK.AVG
t
CK.AVG
ns
ns
nCK
nCK
35)
35)
35)36)
t
XP
2
—
nCK
t
XSNR
t
XSRD
WL
t
RFC
+10
200
RL–1
—
—
ns
nCK
nCK
35)
Parameter
Symbol
DDR2–667
Unit
Notes
1)2)3)4)5)6)
7)8)
Min.
Max.
相關(guān)PDF資料
PDF描述
HYS72T1G242EP-3S-C 240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T256000ER 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-3.7-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 240-Pin Registered DDR2 SDRAM Modules
HYS72T256020EU-2.5-B 240-Pin unbuffered DDR2 SDRAM Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T1G242EP-3S-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual Die Registered DDR2 SDRAM Modules
HYS72T256000ER 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-3.7-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000ER-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T256000HR 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
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