參數(shù)資料
型號: HYS72T128020HU-3S-A
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 240-Pin Unbuffered DDR2 SDRAM Modules
中文描述: 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240
封裝: GREEN, DIMM-240
文件頁數(shù): 32/76頁
文件大?。?/td> 1840K
代理商: HYS72T128020HU-3S-A
Internet Data Sheet
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
32
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
Chapter contains current tables for each of the product types and the definitions of the various currents.
Table 22 “IDD Measurement Conditions” on Page 32
Table 23 “Definitions for IDD” on Page 33
Table 24 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A” on Page 34
Table 25 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A” on Page 35
Table 26 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A” on Page 36
TABLE 22
I
DD
Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
One bank Active - Precharge;
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK.MIN
,
t
RC
=
t
RC.MIN
,
t
RAS
=
t
RAS.MIN
,
t
RCD
=
t
RCD.MIN
, AL = 0, CL = CL
MIN
; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK.MIN
; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX
,
t
RP
=
t
RP.MIN
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I
OUT
= 0 mA.
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open;
t
CK
=
t
CK.MIN
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CKMIN
;
t
RAS
=
t
RASMAX
;
t
RP
=
t
RPMIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING;
I
OUT
= 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
MIN
;
t
CK
=
t
CK.MIN
;
t
RAS
=
t
RAS.MAX.
,
t
RP
=
t
RP.MAX
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
I
DD0
I
DD1
6)
I
DD2N
I
DD2P
I
DD2Q
I
DD3N
I
DD3P(0)
I
DD3P(1)
I
DD4R
6)
I
DD4W
I
DD5B
相關PDF資料
PDF描述
HYS72T64000HU-3.7-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T64000HU-3-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T64000HU-3S-A 240-Pin Unbuffered DDR2 SDRAM Modules
HYS72T128300HP-3.7-A 240-Pin Registered DDR2 SDRAM Modules
HYS72T128300HP-3S-A 240-Pin Registered DDR2 SDRAM Modules
相關代理商/技術參數(shù)
參數(shù)描述
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HYS72T128020HU-5-B 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128300HP-3.7-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules
HYS72T128300HP-3S-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules