參數(shù)資料
型號： HYS72T128001HR
廠商： QIMONDA
英文描述： 240-Pin Registered DDR SDRAM Modules
中文描述： 240針DDR SDRAM內(nèi)存模塊注冊
文件頁數(shù)： 26/40頁
文件大小： 1050K
代理商： HYS72T128001HR
Internet Data Sheet
Rev. 1.4, 2007-02
03062006-GD6J-14FP
26
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
TABLE 15
ODT AC Characteristics and Operating Conditions for DDR2-667
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
t
AON
t
AONPD
t
AOFD
t
AOF
t
AOFPD
t
ANPD
t
AXPD
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
2
t
AC.MIN
t
AC.MIN
+ 2 ns
2.5
t
AC.MIN
t
AC.MIN
+ 2 ns
3
8
2
t
AC.MAX
+ 0.7 ns
2
t
CK +
t
AC.MAX
+ 1 ns
2.5
t
AC.MAX
+ 0.6 ns
2.5
t
CK +
t
AC.MAX
+ 1 ns
—
—
n
CK
ns
ns
n
CK
ns
ns
n
CK
n
CK
1)
1) New units, “t
” and “
n
”, are introduced in DDR2-667 and DDR2-800. Unit “
t
” represents the actual
t
of the input clock
under operation. Unit “
n
CK
” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “
t
CK
” is used for both concepts. Example:
t
XP
= 2 [
n
CK
] means; if Power Down exit is registered at
T
m
, an Active command may
be registered at
T
m
+ 2, even if (
T
m
+ 2 -
T
m
) is 2 x
t
CK.AVG
+
t
ERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
, which is interpreted differently per speed bin. For DDR2-667/800,
t
AOND
is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD
, which is interpreted differently per speed bin. For DDR2-667/800, if
t
CK(avg)
= 3 ns is assumed,
t
AOFD
is 1.5 ns
(= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual
input clock edges.
1)2)
1)
1)
1)3)
1)
1)
1)
相關PDF資料
PDF描述
HYS72T128001HR-5-A 240-Pin Registered DDR SDRAM Modules
HYS72T256000HR 240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3.7-A 240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-3S-A 240-Pin Registered DDR SDRAM Modules
HYS72T256000HR-5-A 240-Pin Registered DDR SDRAM Modules
相關代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72T128001HR-5-A 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules
HYS72T128020EU-2.5-B2 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-25F-B2 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-3.7-B2 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
HYS72T128020EU-3-B2 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin unbuffered DDR2 SDRAM Modules
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