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參數(shù)資料
| 型號： | HYS72T128000HR-3-A |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | GREEN, DIMM-240 |
| 文件頁數(shù)： | 31/74頁 |
| 文件大?。?/td> | 1554K |
| 代理商： | HYS72T128000HR-3-A |
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Internet Data Sheet
Rev. 1.31, 2006-11
03292006-21GC-MK06
31
HYS72T[64/128/256]xx0HR–[3/3S/3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 21
Definitions for I
DD
Burst Refresh Current
t
CK
=
t
CK.MIN
., Refresh command every
t
RFC
=
t
RFC.MIN
interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Distributed Refresh Current
t
CK
=
t
CK.MIN
, Refresh command every
t
RFC
=
t
REFI
interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Self-Refresh Current
CKE
≤
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
FLOATING, Data bus inputs are FLOATING. RESET is LOW.
I
DD6
current values are
guaranteed up to
T
CASE
of 85
°
C max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4.
Control and address bus inputs are STABLE during DESELECTS.
I
OUT
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for
I
DD
see
Table 21
4)
I
,
I
and
I
current measurements are defined with the outputs disabled (
I
= 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode
I
DD2P
6) RESET signal is HIGH for all currents, except for
I
DD6
(Self Refresh)
7) All current measurements includes Register and PLL current consumption
8) For details and notes see the relevant Qimonda component data sheet
I
DD5B
I
DD5D
I
DD6
I
DD7
Parameter
Description
LOW
STABLE
FLOATING
SWITCHING
V
IN
≤
V
IL(ac).MAX
, HIGH is defined as
V
IN
≥
V
IH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are
V
REF
=
V
DDQ
/2
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Parameter
Symbol
Note
1)2)3)4)5)6)7)8)
相關PDF資料 |
PDF描述 |
|---|---|
| HYS72T128020HU-2.5-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020HU-25F-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020HU-3.7-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020HU-3-B | 240-Pin unbuffered DDR2 SDRAM Modules |
| HYS72T128020HU-3S-B | 240-Pin unbuffered DDR2 SDRAM Modules |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T128000HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128000HR-3S-B | 功能描述:MODULE DDR2 1GB 240-DIMM RoHS:是 類別:存儲卡，模塊 >> 存儲器 - 模塊 系列:- 標準包裝:100 系列:- 存儲器類型:SDRAM 存儲容量:1GB 速度:133MHz 特點:- 封裝/外殼:168-DIMM |
| HYS72T128000HR-5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128000HR-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128001HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR SDRAM Modules |
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