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| 型號(hào)： | HYS72T128000HP-3S-B |
| 廠商： | QIMONDA AG |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 240-Pin Registered DDR2 SDRAM Modules |
| 中文描述： | 128M X 72 DDR DRAM MODULE, 0.45 ns, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁(yè)數(shù)： | 20/65頁(yè) |
| 文件大?。?/td> | 1429K |
| 代理商： | HYS72T128000HP-3S-B |
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Internet Data Sheet
Rev. 1.1, 2007-03
03292006-EO3M-LEK7
20
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e.
t
,
t
, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing
t
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
V
level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
V
level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
V
il(DC)MAX
and
V
ih(DC)MIN
. See
Figure 3
.
19) If
t
DS
or
t
DH
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21)
t
is the minimum of the absolute half period of the actual input clock.
t
is an input parameter but not an input specification parameter.
It is used in conjunction with t
QHS
to derive the DRAM output timing
t
QH
. The value to be used for
t
QH
calculation is determined by the
following equation;
t
= MIN (
,
t
), where,
t
CH.ABS
is the minimum of the actual instantaneous clock high time;
t
CL.ABS
is the
minimum of the actual instantaneous clock low time.
22)
t
and
t
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (
t
HZ
), or begins driving (
t
LZ
) .
23) Input waveform timing is referenced from the input signal crossing at the
V
IL.DC
level for a rising signal and
V
IH.DC
for a falling signal applied
to the device under test. See
Figure 4
.
24) Input waveform timing is referenced from the input signal crossing at the
V
IH.AC
level for a rising signal and
V
IL.AC
for a falling signal applied
to the device under test. See
Figure 4
.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
t
,
t
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26)
t
QH
=
t
HP
–
t
QHS
, where:
t
HP
is the minimum of the absolute half period of the actual input clock; and
t
QHS
is the specification value under
the max column. {The less half-pulse width distortion present, the larger the
t
value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides
t
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 975 ps minimum. 2) If the system
provides
t
HP
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
t
QH
of 1080 ps minimum.
27)
t
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
t
at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28)
t
RPST
end point and
t
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
), or begins driving (
t
).
Figure 2
shows a method to calculate these points when the device is no longer driving (
t
), or begins
driving (
t
RPRE
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
=
t
+
t
= 0.9 x
t
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
=
t
+
t
= 0.4 x
t
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
31) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
t
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP
= 15 ns, the device will support
t
= RU{
t
/
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
32)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T128020HP-2.5-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HP-25F-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HP-3.7-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HP-3-B | 240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128020HP-3S-B | 240-Pin Registered DDR2 SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T128000HR | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules |
| HYS72T128000HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128000HR-3.7-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T128000HR-37-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDR2 Registered Memory Modules |
| HYS72T128000HR-3-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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