參數(shù)資料
型號(hào)： HYS72D64320HBR-6-C
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 184-Pin Registered Double Data Rate SDRAM Module
中文描述： 64M X 72 DDR DRAM MODULE, 0.7 ns, DMA184
封裝： GREEN, DIMM-184
文件頁(yè)數(shù)： 18/50頁(yè)
文件大?。?/td> 1158K
代理商： HYS72D64320HBR-6-C
Internet Data Sheet
Rev. 1.32, 2007-03
03292006-Q22P-G7TH
18
HYS72D[128/64/32]3xx[G/H]BR–[5/6/7]–C
Registered Double Data Rate SDRAM
Address and control input setup time
t
IS
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)7)
0.7
—
0.8
—
ns
slow slew rate
3)4)5)6)7)
Data-out low-impedance time from
CK/CK
Mode register set command cycle
time
DQ/DQS output hold time
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh
command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
t
WTR
Exit self-refresh to non-read
command
Exit self-refresh to read command
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V (DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock cycle time.
7) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between
V
IH(ac)
and
V
IL(ac)
.
8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
t
LZ
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)6)
t
MRD
2
—
2
—
t
CK
2)3)4)5)
t
QH
t
QHS
t
RAP
t
RAS
t
RC
t
HP
–
t
QHS
—
t
RCD
40
55
—
+0.50
—
70E+3
—
t
HP
–
t
QHS
—
t
RCD
42
60
—
+0.50
—
70E+3
—
ns
ns
ns
ns
ns
2)3)4)5)
TFBGA
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
RCD
t
REFI
t
RFC
15
—
65
—
7.8
—
18
—
72
—
7.8
—
ns
μ
s
ns
2)3)4)5)
2)3)4)5)9)
2)3)4)5)
t
RP
t
RPRE
t
RPST
t
RRD
15
0.9
0.40
10
—
1.1
0.60
—
18
0.9
0.40
12
—
1.1
0.60
—
ns
t
CK
t
CK
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
WPRE
t
WPRES
t
WPST
t
WR
0.25
0
0.40
15
2
75
—
—
0.60
—
—
—
0.25
0
0.40
15
1
75
—
—
0.60
—
—
—
t
CK
ns
t
CK
ns
t
CK
ns
2)3)4)5)
2)3)4)5)8)
2)3)4)5)8)
2)3)4)5)
2)3)4)5)
t
XSNR
2)3)4)5)
t
XSRD
200
—
200
—
t
CK
2)3)4)5)
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition
1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
相關(guān)PDF資料
PDF描述
HYS72D64300HU-5-C 184-Pin Unbuffered Double Data Rate SDRAM
HYS72D64300HU-6-C 184-Pin Unbuffered Double Data Rate SDRAM
HYS72D64301HBR_07 184-Pin Registered Double-Data-Rate SDRAM Module
HYS72D64301HBR-5-C 184-Pin Registered Double-Data-Rate SDRAM Module
HYS72D64301HBR-6-C 184-Pin Registered Double-Data-Rate SDRAM Module
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72D64320HU-5-C 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
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HYS72D64500GR-7-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx72) PC2100 1-bank?
HYS72D64500GR-7-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Low Profile Registered DDR-I SDRAM-Modules
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