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參數(shù)資料
| 型號(hào)： | HYS72D64301GBR-6-B |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 184 - Pin Registered Double-Data-Rate SDRAM Module |
| 中文描述： | 64M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | RDIMM-184 |
| 文件頁數(shù)： | 22/51頁 |
| 文件大?。?/td> | 1115K |
| 代理商： | HYS72D64301GBR-6-B |
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Internet Data Sheet
Rev. 1.42, 2007-01
03292006-7CZA-YS85
22
HYS72D[64/128/256]xxx[G/H]BR–[5/6/7]–B
Registered DDR SDRAM Module
Active to Read w/AP delay
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh command period
t
RFC
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B command
Write preamble
Write preamble setup time
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
1)
V
DDQ
= 2.5 V
±
0.2 V, VDD = +2.5 V
±
0.2 V ; 0
°
C
≤
T
A
≤
70
°
C
2) Input slew rate
≥
1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock cycle time.
7)
t
and
t
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between
V
IH(ac)
and
V
IL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on
t
DQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
13) In all circumstances,
t
XSNR
can be satisfied using
t
XSNR
= tRFC,min + 1
×
t
CK
t
RAP
t
RAS
t
RC
t
RCD
t
REFI
t
RCD
45
65
20
7.8
75
20
0.9
0.4
15
0.25
0
0.4
15
1
75
200
—
120E+3
—
—
—
—
—
1.1
0.6
—
—
—
—
—
—
—
—
ns
ns
ns
ns
μ
s
ns
ns
t
CK
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
ns
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)10)
2)3)4)5)
t
RP
t
RPRE
t
RPST
t
RRD
t
WPRE
t
WPRES
t
WPST
t
WR
t
WTR
t
XSNR
t
XSRD
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
2)3)4)5)
Parameter
Symbol
–7
Unit
Note/Test
Condition
1)
DDR266A
Min.
Max.
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| HYS72D64301HBR-5-B | 184 - Pin Registered Double-Data-Rate SDRAM Module |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64301HBR_07 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D64301HBR-5-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D64301HBR-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D64301HBR-6-B | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184 - Pin Registered Double-Data-Rate SDRAM Module |
| HYS72D64301HBR-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double-Data-Rate SDRAM Module |
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