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參數資料
| 型號： | HYS64D64020GU-8-B |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| 中文描述： | 184引腳緩沖雙列內存模組 |
| 文件頁數： | 19/51頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | HYS64D64020GU-8-B |
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Data Sheet
19
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 10
Parameter
Operating Current 0
one bank; active/ precharge;
t
RC
=
t
RC,MIN
;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE
≤
V
IL,MAX
Precharge Floating Standby Current
CS
≥
V
IH,,MIN
, all banks idle; CKE
≥
V
IH,MIN
;
address and other control inputs changing once per clock cycle;
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current
CS
≥
V
IHMIN
, all banks idle; CKE
≥
V
IH,MIN
;
address and other control inputs stable at
≥
V
IH,MIN
or
≤
V
IL,MAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Power-Down Standby Current
one bank active; power-down mode; CKE
≤
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current
one bank active; CS
≥
V
IH,MIN
; CKE
≥
V
IH,MIN
;
t
RC
=
t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
= 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
=
t
RFCMIN
, distributed refresh
Self-Refresh Current
CKE
≤
0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
I
DD
Conditions
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HYS64D64020HBDL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
| HYS64D64020HBDL-5-C | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
| HYS64D64020HBDL-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
| HYS64D64020HDL-5-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules |
| HYS64D64020HDL-5-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:200-Pin Small-Outline Dual-In-Line Memory Modules |
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