參數(shù)資料
型號(hào): HYNET
英文描述: hyNet 32XS 1-page product brief
中文描述: hyNet 32XS 1頁(yè)產(chǎn)品簡(jiǎn)介
文件頁(yè)數(shù): 2/2頁(yè)
文件大?。?/td> 72K
代理商: HYNET
hyNet 32XS Block Diagram
Hyperstone AG
Line-Eid-Strasse 3
78467 Konstanz, Germany
Phone:
+49 7531 98030
Fax:
+49 7531 51725
E-mail:
info@hyperstone.de
Web:
www.hyperstone.com
Hyperstone Taiwan
11F, No.183, Sec.2, Tiding Blvd.
Neihu District, Taipei, Taiwan, R.O.C.
Phone:
+886 2 8751 0203
Fax:
+886 2 8797 2321
E-mail:
taiwan@hyperstone.com
Web:
www.hyperstone.com.tw
Content is subject to change without prior notice. hyNet, hyNet 32XS, hyRTK and hyDSP are trademarks of Hyperstone AG. Other brand, product or company names
are property of the respective holder. Warranties, implied or expressed as well as liablities for any damage resulting from using provided information in this document
are excluded until part of a separate written contract.
HS-Mkt-AM-005-04-01
Internal Memory-System
16kByte RAM, two 2kByte instruction/data caches
8kByte Mask ROM (Boot loader)
128kByte SRAM
32kByte Shared SRAM (Ethernet)
32-Bit data and address bus
Key Features
4 internal busses with multi channel DMA controller
o
Peripheral Bus with variable frequency, to reduce
power consumption
o
Multi-master/multi-slave high frequency System Bus
o
Ethernet Bus
o
Coprocessor Bus
Direct Memory Access Controller with 6
independent configurable channels
Memory Management Unit (MMU)
Time Processor Unit (TPU) programmable timer
with one 32-bit counter and two 16 bit counters
Efficient Power Management
Management Unit including reset manager, clock
manager, configuration unit
Interrupt Controller
Galois Factory Coprocessor: hardware calculation
of Galois field operations
Clock Synchronization Core according to IEEE 1588
standard
YUV interface CCIR656-compliant video input
interface reassembling raw video data out of a
CCIR656 YCrCb 4:2:2 8-bit data stream
JTAG (Boundary Scan)
compliant to the IEEE P1149.1
Real Time Clock
Watchdog
Versatile Interfaces
Dual 10/100 Mbit/s Ethernet MAC with two MII and
one Ethernet PHY supporting real-time standard
(IEEE 1588), also fully compliant with Ethernet
standards such as IEEE 802.3, 802.3u, and ANSI
X3.263-1995 (FDDI-TP- PMD)
USB 1.1 device controller with integrated
transceiver, supports up to 12Mbit/s serial data
transmission
PCM Interface connecting to an external IOM-2 bus
Controller Area Network (CAN) Interface,
compatible to CAN 2.0 and extended format, and
Philips SJA1000
Asynchronous Transfer Mode (ATM) – UTOPIA
Level-2 Interface, for connection of up to 3 external
ATM physical layer controller (PHYs)
Multiplexed Processor Interface (MPI) configurable
for CPU independent external transfers, accessible
directly by the CPU or a DMA, connects up to 15
external Power Line physical layer controllers for
TDM transmission
Communication Engine, programmable serial
communication providing 16 I/O lines or software
controlled general purpose I/Os, providing eight
communication channels and commands including
UART, IrDA, I
2
C Master and Slave, Synchronous
Communication and interface options to various
devices such as A/D or D/A converters, codecs and
serial memories
Development Software and Hardware Support
All necessary development software and hardware is available from Hyperstone. Available options include an inexpensive
starter-kit option as well as the Hyperstone real-time kernel (hyRTK), DSP software library (hyDSP), macro assembler,
C-compiler, debugger, file linker, library manager, and profiler.
E1 -32XSR
116kB RAM
MMU
L1 Cache
L2 Cache
SRAM
ROM
System
Bus
Controller
Controller
Interface
BBus Bridge SP
Shared
Bus
Bridge SE
EthEthernet Sub-System
-System:
DMA
DMA
FIFO
MAC 1
MIIS
FIFO
MAC 0
MII
MII
PHY
troller
Mgmt.
Unit
dog
-dog
-Engine
16 GPIO
CAN
MPI
IOM -2
ATM
UTOPIA
YUV
1.1
Trans
Trans
cei-
hyperstone
RISC / DSP
SRAM
128kB
Boot
Boot
I/O, SDRAM
External Bus
Memory,
6 channel DMA
controller
632kB SRAM
-System:
SYN1588
Con -
Bus
Bus
Interrupt
Controller
Com
UART
IrDA,
I2C,
C,
PCM
USB
Trans-
System Bus
RTC
Timer
Peripheral Bus
Galois
Factory
Coprocessor
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