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參數(shù)資料
| 型號： | HYMP112S64MP8-C5 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | SCREW LOCKS MALE |
| 中文描述： | DDR2 SDRAM的SO - DIMM插槽 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 405K |
| 代理商： | HYMP112S64MP8-C5 |
HYMP112S64(L)MP8
Rev. 0.1/ July 2004
16
SERIAL PRESENCE DETECT
Byte#
Function Description
Speed
Grade
all
all
all
all
all
all
all
all
all
E3,E4
C4,C5
E3,E4
C4,C5
all
all
all
all
Function
Supported
128 Bytes
256 Bytes
DDR2 SDRAM
14
10
30.0mm/stack/2rank
64 Bits
-
SSTL 1.8V
5.0 ns
3.75 ns
+/-0.6ns
+/-0.5ns
non-ECC
7.8us & Self refresh
x8
None
-
4,8
4
3, 4, 5
-
SO-DIMM
Normal
-
5.0ns
3.75ns
+/-0.6ns
+/-0.5ns
5.0ns
Undefined
+/-0.6ns
Undefined
15ns
20ns
18.75ns
7.5ns
15ns
20ns
18.75ns
40ns
45ns
512MB
0.6ns
0.5ns
0.6ns
0.5ns
0.40ns
0.35ns
0.40ns
0.35ns
15ns
10ns
7.5ns
7.5ns
Undefined
Undefined
tRC extended
55ns
60ns
65ns
63.75ns
Hexa
Value
80
08
08
0E
0A
71
40
00
05
50
3D
60
50
00
82
08
00
00
0C
04
38
00
04
00
00
50
3D
60
50
50
00
60
00
3C
50
4B
1E
3C
50
4B
28
2D
80
60
50
60
50
40
35
40
35
3C
28
1E
1E
00
00
50
37
3C
41
3F
Note
0
1
2
3
4
5
6
7
8
Number of bytes utilized by module manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of DIMM ranks
Module data width
Module data width (continued)
Voltage Interface level of this assembly
1
1
9
DDR SDRAM cycle time at CL=5
2
2
10
DDR SDRAM access time from clock (tAC)
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type
Refresh Rate and Type
Primary DDR SDRAM width
Error Checking DDR SDRAM data width
Reserved
Burst Lengths Supported
Number of banks on each SDRAM Device
CAS latency supported
Reserved
DIMM Type
DDR SDRAM module attributes
DDR SDRAM device attributes : General
all
all
all
all
all
all
23
DDR SDRAM cycle time at CL=4(tCK)
E3,E4,C5
C4
E3,E4,C5
C4
E3,C4
E4,C5
E3,C4
E4,C5
E3, C4
E4
C5
all
E3, C4
E4
C5
E3
E4,C4,C5
all
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
all
E3, E4
C4, C5
all
2
24
DDR SDRAM access time from clock at CL=4(tAC)
2
25
DDR SDRAM cycle time at CL=3(tCK)
2
26
DDR SDRAM access time from clock at CL=3(tAC)
2
27
Minimum Row Precharge Time(tRP)
28
Minimum Row Activate to Row Active delay(tRRD)
29
Minimum RAS to CAS delay(tRCD)
30
Minimum active to precharge time(tRAS)
31
Module rank density
32
Address and command input setup time before clock (tIS)
33
Address and command input hold time after clock (tIH)
34
Data input setup time before clock (tDS)
35
Data input hold time after clock (tDH)
36
Write recovery time(tWR)
37
Internal write to read command delay(tWTR)
38
39
Internal read to precharge command delay(tRTP)
Memory analysis probe characteristics
40
Extension of byte 41 tRC and byte 42 tRFC
E3,E4,C4
C5
E3
C4
E4
C5
41
Minimum active / auto-refresh time ( tRC)
Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4),
C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)
相關PDF資料 |
PDF描述 |
|---|---|
| HYMP112S64MP8-E3 | SCREW LOCKS MALE |
| HYMP112S64MP8-E4 | SCREW LOCKS FEMALE SETS |
| HYS72D64300HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-7-C | 184-Pin Registered Double Data Rate SDRAM Module |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112S64MP8-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver. |
| HYMP112S64MP8-E4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
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