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| 型號(hào)： | HYMP112S64MP8-C4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | SCREW LOCKS MALE |
| 中文描述： | 128M X 64 DDR DRAM MODULE, 0.5 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, DIMM-200 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 405K |
| 代理商： | HYMP112S64MP8-C4 |
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HYMP112S64(L)MP8
Rev. 0.1/ July 2004
3
PIN Functional Description
Symbol
Type
Polarity
Pin Description
CK[1:0],
CK[1:0]
Input
Cross Point
The system clock inputs. All adress an commands lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
CKE[1:0]
Input
Active High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
/S[1:0]
Input
Active Low
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
/RAS, /CAS,
/WE
Input
Active Low
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS
and WE define the operation to be excecuted by the SDRAM.
BA[1:0]
Input
Selects which DDR2 SDRAM internal bank of four or eight is activated.
ODT[1:0]
Input
Active High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
A[9:0], A10/
AP, A[15:11]
Input
During a Bank Activate command cycle, difines the row address when sampled at the cross
point of the rising edge of CK and falling edge of CK. During a Read or Write command
cycle, defines the column address when sampled at the cross point of the rising edge of CK
and falling edge of CK. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge
is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of
the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to
precharge.
DQ[63:0]
In/Out
Data Input/Output pins.
DM[7:0]
Input
Active High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
DQS[7:0],
DQS[7:0]
In/Out
Cross point
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of
the data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed approriately.
RESET
Input
Active Low
When hign, the PLL outputs are always driven when the PLL input clock is active. When
low, the PLL remains locked on the input clock, if active, but output clocks are stopped.
Pulled high via 10K resistor on the SO-DIMM . Only used on DDR2 SO-DIMMs with a
PLL.
V
DD
,
V
DD
SPD,V
SS
Supply
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
SDA
In/Out
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD t
o act as a pull up.
SCL
Input
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to VDD to act as a pull up.
SA[1:0]
Input
Address pins used to select the Serial Presence Detect base address.
TEST
In/Out
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYMP112S64MP8-C5 | SCREW LOCKS MALE |
| HYMP112S64MP8-E3 | SCREW LOCKS MALE |
| HYMP112S64MP8-E4 | SCREW LOCKS FEMALE SETS |
| HYS72D64300HBR-5-C | 184-Pin Registered Double Data Rate SDRAM Module |
| HYS72D64300HBR-6-C | 184-Pin Registered Double Data Rate SDRAM Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYMP112S64MP8-C5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112S64MP8-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver. |
| HYMP112S64MP8-E4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:DDR2 SDRAM SO-DIMM |
| HYMP112U64CP8-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
| HYMP112U64CP8-S5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:240pin DDR2 SDRAM Unbuffered DIMMs |
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