參數(shù)資料
型號： HYB18T512400AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 58/117頁
文件大小： 2102K
代理商： HYB18T512400AF-3
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
58
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
3.22
Precharge Command
The Precharge Command is used to precharge or close
a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are
LOW and CAS is HIGH at the rising edge of the clock.
The Pre-charge Command can be used to precharge
each bank independently or all banks simultaneously. 3
address bits A10, BA[1:0] are used to define which
bank to precharge when the command is issued.
Note:The bank address assignment is the same for activating and precharging a specific bank.
3.22.1
The following rules apply as long as the
t
RTP
timing
parameter - Internal Read to Precharge Command
delay time - is less or equal two clocks, which is the
case for operating frequencies less or equal 266 MHz
(DDR2 400 and 533 speed sorts).
Minimum Read to Precharge command spacing to the
same bank = AL + BL/2 clocks. For the earliest possible
precharge, the Precharge command may be issued on
the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the
minimum
t
RAS
timing is satisfied.
Read Followed by a Precharge
The term (t
RTP
- 2
×
t
CK
) is 0 clocks for operating
frequencies less or equal 266 MHz (DDR2-400 and
DDR2-533 product speed sorts). The term (t
RTP
- 2
×
t
CK
)
is one clock for frequencies higher then 266 MHz
(DDR2-667 speed sort).
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
t
RP
) has been satisfied
from the clock at which the precharge begins.
2. The RAS cycle time (
t
RC.MIN
) from the previous bank
activation has been satisfied.
Figure 40
Read Operation Followed by Precharge Example 1
RL = 4 (AL = 1, CL = 3), BL = 4,
t
RTP
≤
2 CKs
Table 17
A10
0
0
0
0
1
Bank Selection for Precharge by Address Bits
BA1
0
0
1
1
Don’t Care
BA0
0
1
0
1
Don’t Care
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
all banks
NOP
Precharge
NOP
Bank A
Activate
NOP
NOP
READ A
Posted CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
BR-P413
NOP
AL + BL/2 clks
Dout A0
Dout A1
Dout A2
Dout A3
AL = 1
CL = 3
RL = 4
>=tRAS
CL = 3
tRP
DQS,
DQS
NOP
>=tRC
>=tRTP
CK, CK
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參數(shù)描述
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HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF)
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