參數(shù)資料
型號: HY5PS1G831LF
廠商: Hynix Semiconductor Inc.
英文描述: 1Gb DDR2 SDRAM
中文描述: 1G DDR2內(nèi)存
文件頁數(shù): 30/33頁
文件大?。?/td> 540K
代理商: HY5PS1G831LF
Rev. 1.2 / Dec 2006
30
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
9. tIS and tIH (input setup and hold) derating
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
REF
(dc) and the first crossing of V
IH
(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of V
(dc) and the first crossing of V
(ac)max. If the actual signal
is always earlier than the nominal slew rate for line between shaded ‘V
(dc) to ac region’, use nominal
slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘V
(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac
level to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of V
(dc). Hold(tIH) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of V
REF
(dc). If the actual signal signal is always later than the nom-
inal slew rate line between shaded ‘dc to V
(dc) region’, use nominal slew rate for derating value(see
Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
V
REF
(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to V
REF
(dc) level is
used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
V
(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transi-
tion and reach V
IH/IL
(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpola-
tion.
tIS
tIH
tIS
tIH
tIS
tIH
Units
Notes
4.0
+187
+94
TBD
TBD
TBD
TBD
ps
1
3.5
+179
+89
TBD
TBD
TBD
TBD
ps
1
3.0
+167
+83
TBD
TBD
TBD
TBD
ps
1
2.5
+150
+75
TBD
TBD
TBD
TBD
ps
1
2.0
+125
+45
TBD
TBD
TBD
TBD
ps
1
1.5
+83
+21
TBD
TBD
TBD
TBD
ps
1
1.0
+0
0
TBD
TBD
TBD
TBD
ps
1
0.9
-11
-14
TBD
TBD
TBD
TBD
ps
1
0.8
-25
-31
TBD
TBD
TBD
TBD
ps
1
0.7
-43
-54
TBD
TBD
TBD
TBD
ps
1
0.6
-67
-83
TBD
TBD
TBD
TBD
ps
1
0.5
-100
-125
TBD
TBD
TBD
TBD
ps
1
0.4
-150
-188
TBD
TBD
TBD
TBD
ps
1
0.3
-223
-292
TBD
TBD
TBD
TBD
ps
1
0.25
-250
-375
TBD
TBD
TBD
TBD
ps
1
0.2
-500
-500
TBD
TBD
TBD
TBD
ps
1
0.15
-750
-708
TBD
TBD
TBD
TBD
ps
1
0.1
-1250
-1125
TBD
TBD
TBD
TBD
ps
1
tIS, tIH Derating Values
Differential Slew Rate
Command /
Address
Slew
rate(V/ns)
2.0 V/ns
CK, CK
1.5 V/ns
1.0 V/ns
相關(guān)PDF資料
PDF描述
HY5PS1G831LF-C4 1Gb DDR2 SDRAM
HY5PS1G831LF-C5 1Gb DDR2 SDRAM
HY5PS1G831LF-E3 1Gb DDR2 SDRAM
HY5PS1G831LF-E4 1Gb DDR2 SDRAM
HY5PS1G831LF-Y5 1Gb DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5PS1G831LF-C4 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM
HY5PS1G831LF-C5 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM
HY5PS1G831LF-E3 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM
HY5PS1G831LF-E4 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM
HY5PS1G831LF-Y5 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM