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參數(shù)資料
| 型號： | HY5PS1G831LF-E4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM |
| 中文描述： | 128M X 8 DDR DRAM, 0.5 ns, PBGA68 |
| 封裝： | FBGA-68 |
| 文件頁數(shù)： | 32/33頁 |
| 文件大?。?/td> | 540K |
| 代理商： | HY5PS1G831LF-E4 |
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Rev. 1.2 / Dec 2006
32
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
ure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driv-
ing (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the V
IH
(ac) level to the differential data strobe crosspoint for a rising signal, and from the
input signal crossing at the V
IL
(ac) level to the differential data strobe crosspoint for a falling signal applied
to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the V
IH
(dc) level to the differential data strobe crosspoint for a rising signal and V
IL
(dc) to
the differential data strobe crosspoint for a falling signal applied to the device under test.
22. Input waveform timing is referenced from the input signal crossing at the V
IH
(ac) level for a rising signal
and V
IL
(ac) for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the V
IL
(dc) level for a rising signal
and V
IH
(dc) for a falling signal applied to the device under test.
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
VOH + xmV
VOH + 2xmV
VOL + 1xmV
VOL + 2xmV
tHZ
tRPST end point
VTT + 2xmV
VTT + xmV
VTT -xmV
VTT - 2xmV
tHZ
tRPRE begin point
DQS
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
tDH
tDS
DQS
V
REF
(dc)
V
IL(dc)
max
V
SS
V
IL(ac)
max
tDH
tDS
Differential Input waveform timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5PS1G831LF-Y5 | 1Gb DDR2 SDRAM |
| HY5PS1G831LF-Y6 | 1Gb DDR2 SDRAM |
| HY5S6B6D | 4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DLF-BE | 4Banks x1M x 16bits Synchronous DRAM |
| HY5S6B6DLFP-BE | 4Banks x1M x 16bits Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5PS1G831LF-Y5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G831LF-Y6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS2G431AMP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2Gb DDR2 SDRAM(DDP) |
| HY5PS2G431AMP-C4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2Gb DDR2 SDRAM(DDP) |
| HY5PS2G431AMP-E3 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:2Gb DDR2 SDRAM(DDP) |
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