參數(shù)資料
型號(hào): HY5PS1G831LF-C5
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 1Gb DDR2 SDRAM
中文描述: 128M X 8 DDR DRAM, 0.45 ns, PBGA68
封裝: FBGA-68
文件頁(yè)數(shù): 22/33頁(yè)
文件大?。?/td> 540K
代理商: HY5PS1G831LF-C5
Rev. 1.2 / Dec 2006
22
1
HY5PS1G431(L)F
1
HY5PS1G831(L)F
-Continued
Parameter
Symbol
DDR2-667
Unit
Note
min
max
Four Active Window for 2KB page size products
tFAW
50
-
ns
CAS to CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
-
ns
Auto precharge write recovery + precharge time
tDAL
WR+tRP
-
tCK
14
Internal write to read command delay
tWTR
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
ns
3
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
tCK
Exit precharge power down to any non-read command
tXP
2
-
tCK
Exit active power down to read command
tXARD
2
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
1, 2
CKE minimum pulse width
(high and low pulse width)
t
CKE
3
tCK
ODT turn-on delay
t
AOND
2
2
tCK
ODT turn-on
t
AON
tAC(min)
tAC(max)+0.7
ns
6,16
ODT turn-on(Power-Down mode)
t
AONPD
tAC(min)+2
2tCK+tAC(max)
+1
ns
ODT turn-off delay
t
AOFD
2.5
2.5
tCK
ODT turn-off
t
AOF
tAC(min)
tAC(max)+ 0.6
ns
17
ODT turn-off (Power-Down mode)
t
AOFPD
tAC(min)+2
2.5tCK+tAC(ma
x)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
ns
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK+tIH
ns
15
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