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| 型號： | HY5DU56822DLTP-M |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| 中文描述： | 32M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 414K |
| 代理商： | HY5DU56822DLTP-M |
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Rev. 0.1 /May 2004 18
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
Operating Mode
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
1.5
1
1
0
2.5
1
1
1
Reserved
BA0
MRS Type
0
MRS
1
EMRS
A12~A9
A8
A7
A6~A0
Operating Mode
0
0
0
Valid
Normal Operation
0
1
0
Valid
Normal Operation/ Reset DLL
0
0
1
VS
Vendor specific Test Mode
-
-
-
All other states reserved
相關(guān)PDF資料 |
PDF描述 |
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| HY5DU56822DLTP-X | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-H | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-J | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-K | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56822DLTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM |
| HY5DU56822DTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-J | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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