參數(shù)資料
型號(hào): HY5DU56822DLTP-L
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
中文描述: 32M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁(yè)數(shù): 22/37頁(yè)
文件大小: 414K
代理商: HY5DU56822DLTP-L
Rev. 0.1 /May 2004 22
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
ABSOLUTE MAXIMUM RATINGS
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. V
REF
is expected to be equal to 0.5*V
DDQ
of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on V
REF
may not exceed +/- 2% of the dc value.
4. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the
entire temper ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it
represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation
in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source
voltages from 0.1 to 1.0.
6. VIN=0 to VDD, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to VDD
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
0 ~ 70
o
C
o
C
V
V
V
mA
W
Storage Temperature
T
STG
-55 ~ 125
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature
Time
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1
260
10
o
C
sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
2.3
2.3
2.5
2.5
-
-
V
REF
2.7
2.7
V
V
V
V
V
1
V
REF
+ 0.15
-0.3
V
REF
- 0.04
VDDQ/2 -
50mV
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
VDDQ/2 +
50mV
2
Reference Voltage
V
REF
VDDQ/2
V
3
Input Voltage Level, CK and CK
inputs
Input Differential Voltage, CK and
CK inputs
V-I Matching: Pullup to Pulldown
Current Ratio
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
VIN(DC)
-0.3
VDDQ+0.3
V
VID(DC)
0.36
VDDQ+0.6
V
4
VI(RATIO)
0.71
1.4
-
5
I
LI
I
LO
V
OH
V
OL
-2
-5
2
5
-
uA
uA
V
V
6
V
TT
+ 0.76
-
I
OL
= -15.2mA
I
OL
= +15.2mA
V
TT
- 0.76
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