參數(shù)資料
型號： HY5DU56422DTP
廠商： Hynix Semiconductor Inc.
英文描述： 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
中文描述： 256M DDR內(nèi)存（268435456位CMOS雙數(shù)據(jù)速率（DDR）同步DRAM）
文件頁數(shù)： 29/37頁
文件大?。?/td> 414K
代理商： HY5DU56422DTP
Rev. 0.1 /May 2004 29
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
AC Overshoot/Undershoot Specification for Address and Control Pins
This specification is intended for devices with no clamp protection and is guaranteed by design
Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins
Parameter
Specification
DDR333
DDR200/266
Maximum peak amplitude allowed for overshoot (See Figure 1):
1.5V
1.5V
Maximum peak amplitude allowed for undershoot (See Figure 1):
1.5V
1.5V
The area between the overshoot signal and VDD must be less than or equal to (See Figure 1):
4.5V - ns
4.5V - ns
The area between the undershoot signal and GND must be less than or equal to (See Figure 1):
4.5V - ns
4.5V - ns
Parameter
Specification
DDR333
DDR200/266
Maximum peak amplitude allowed for overshoot (See Figure 2):
1.2V
1.2V
Maximum peak amplitude allowed for undershoot (See Figure 2):
1.2V
1.2V
The area between the overshoot signal and VDD must be less than or equal to (See Figure 2):
2.4V - ns
2.4V - ns
The area between the undershoot signal and GND must be less than or equal to (See Figure 2):
2.4V - ns
2.4V - ns
V
DD
0
1
2
3
4
5
6
0
+1
+2
+3
+4
+5
-1
-2
-3
Volts
(V)
Time(ns)
Undershoot
Ground
Max. area=4.5V-ns
Overshoot
Max. amplitude=1.5V
Figure 1: Address and Control AC Overshoot and Undershoot Definitio
V
DD
0
1
2
3
4
5
6
0
+1
+2
+3
+4
+5
-1
-2
-3
Volts
(V)
Time(ns)
Undershoot
Ground
Max. area=2.4V-ns
Overshoot
Max. amplitude=1.2V
Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition
相關(guān)PDF資料
PDF描述
HY5DU56422DTP-H 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-J 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-K 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-L 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-M 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU56422DTP-H 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-J 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-K 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-L 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DTP-M 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
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