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參數(shù)資料
| 型號(hào)： | HY5DU56422DTP-K |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| 中文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大?。?/td> | 414K |
| 代理商： | HY5DU56422DTP-K |
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Rev. 0.1 /May 2004 8
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
Device Deselect
H
X
H
X
X
X
X
1
No Operation
L
H
H
H
Bank Active
H
X
L
L
H
H
RA
V
1
Read
H
X
L
H
L
H
CA
L
V
1
Read with Autoprecharge
H
1,3
Write
H
X
L
H
L
L
CA
L
V
1
Write with Autoprecharge
H
1,4
Precharge All Banks
H
X
L
L
H
L
X
H
X
1,5
Precharge selected Bank
L
V
1
Read Burst Stop
H
X
L
H
H
L
X
1
Auto Refresh
H
H
L
L
L
H
X
1
Self Refresh
Entry
H
L
L
L
L
H
X
1
Exit
L
H
H
X
X
X
1
L
H
H
H
Precharge Power
Down Mode
Entry
H
L
H
X
X
X
X
1
L
H
H
H
1
Exit
L
H
H
X
X
X
1
L
H
H
H
1
Active Power
Down Mode
Entry
H
L
H
X
X
X
X
1
L
V
V
V
1
Exit
L
H
X
1
Note :
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DTP-L | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-M | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-X | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DLTP | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DLTP-H | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422DTP-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64Mx4|2.5V|8K|K/H/L|DDR SDRAM - 256M |
| HY5DU56422LT-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X16MX4|CMOS|TSSOP|66PIN|PLASTIC |
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