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參數(shù)資料
| 型號(hào)： | HY5DU56422DLTP-L |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| 中文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66 |
| 文件頁數(shù)： | 2/37頁 |
| 文件大?。?/td> | 414K |
| 代理商： | HY5DU56422DLTP-L |
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DESCRIPTION
The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double
Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory
density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V +/- 0.2V
PRELIMINARY
Rev. 0.2 / July 2003 3
HY5DU56422D(L)TP
HY5DU56822D(L)TP
HY5DU561622D(L)TP
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 1.5, 2, 2.5 and 3
supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
tRAS Lock-out function supported
Auto refresh and Self refresh supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch (Lead free package)
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* X means speed grade
Part No.
Configuratio
n
Package
HY5DU56422D(L)TP-X*
64Mx4
400mil
66pin
TSOP-II
(Lead-
free)
HY5DU56822D(L)TP-X*
32Mx8
HY5DU561622D(L)TP-X*
16Mx16
OPERATING FREQUENCY
Grade
CL2
CL2.5
Remark
(CL-tRCD-tRP)
- J
133MHz
166MHz
DDR333 (2.5-3-3)
- M
133MHz
133MHz
DDR266 (2-2-2)
- K
133MHz
133MHz
DDR266A (2-3-3)
- H
100MHz
133MHz
DDR266B (2.5-3-3)
- L
100MHz
125MHz
DDR200 (2-2-2)
* CL1.5 @ DDR200 supported
* CL3 supported
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DLTP-M | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-X | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-H | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DTP-J | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422DLTP-M | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM |
| HY5DU56422DT-H | 制造商:Hynix Semi 功能描述: |
| HY5DU56422DTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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