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參數(shù)資料
| 型號： | HY5DS113222FMP-33 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 512M(16Mx32) GDDR SDRAM |
| 中文描述： | 16M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, MO-205DAE, FBGA-144 |
| 文件頁數(shù)： | 27/30頁 |
| 文件大小： | 431K |
| 代理商： | HY5DS113222FMP-33 |
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Rev. 0.1 / Oct. 2004
27
HY5DS113222FM(P)
AC CHARACTERISTICS - I (continue)
N
ote :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
5.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.
7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.
Parameter
Symbol
36
4
Unit
Note
Min
Max
Min
Max
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
CK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
CK
Write DQS Preamble Setup Time
t
WPRES
0
-
0
-
ns
Write DQS Preamble Hold Time
t
WPREH
0.35
-
0.35
-
CK
Write DQS Postamble Time
t
WPST
0.4
0.6
0.4
0.6
CK
Mode Register Set Delay
t
MRD
2
-
2
-
CK
Exit Self Refresh to Any Execute Command
t
XSC
200
-
200
-
CK
4
Power Down Exit Time
t
PDEX
1tCK
+ tIS
-
1tCK
+ tIS
-
CK
Average Periodic Refresh Interval
t
REFI
-
7.8
-
7.8
us
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| HY5DS113222FMP-36 | 512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-4 | 512M(16Mx32) GDDR SDRAM |
| HY5DS283222BF | 128M(4Mx32) GDDR SDRAM |
| HY5DS283222BFP-36 | 128M(4Mx32) GDDR SDRAM |
| HY5DS283222BFP-4 | 128M(4Mx32) GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DS113222FMP-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS113222FMP-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512M(16Mx32) GDDR SDRAM |
| HY5DS283222BF | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DS283222BF-28 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DS283222BF-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
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