參數(shù)資料
型號: HY57V658020BTC-8
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 4 Banks x 2M x 8Bit Synchronous DRAM
中文描述: 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
文件頁數(shù): 8/12頁
文件大?。?/td> 146K
代理商: HY57V658020BTC-8
HY57V658020B
Rev. 1.6/Nov. 01
8
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-75
-8
-10P
-10S
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS Cycle Time
Operation
t
RC
65
-
68
-
70
-
70
-
80
-
ns
Auto Refresh
t
RRC
65
-
68
-
70
-
70
-
96
-
ns
RAS to CAS Delay
t
RCD
20
-
20
-
20
-
20
-
30
-
ns
RAS Active Time
t
RAS
45
100K
48
100K
50
100K
50
100K
50
100K
ns
RAS Precharge Time
t
RP
20
-
20
-
20
-
20
-
30
-
ns
RAS to RAS Bank Active Delay
t
RRD
15
-
16
-
20
-
20
-
20
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-In Delay
t
WTL
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge Command
t
DPL
2
-
2
-
1
-
1
-
1
-
CLK
Data-In to Active Command
t
DAL
5
-
5
-
3
-
3
-
4
-
CLK
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to Data
Output Hi-Z
CAS Latency = 3
t
PROZ3
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2
t
PROZ2
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
t
PDE
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
t
SRE
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
-
64
-
64
-
64
ms
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