參數(shù)資料
型號: HY57V658020B
廠商: Hynix Semiconductor Inc.
英文描述: 4 Banks x 2M x 8Bit Synchronous DRAM
中文描述: 4銀行x 2米× 8位同步DRAM
文件頁數(shù): 7/12頁
文件大?。?/td> 146K
代理商: HY57V658020B
HY57V658020B
Rev. 1.6/Nov. 01
7
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Parameter
Symbol
-75
-8
-10P
-10S
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System clock
cycle time
CAS Latency = 3
tCK3
7.5
1000
8
1000
10
1000
10
1000
10
1000
ns
CAS Latency = 2
tCK2
10
10
10
12
12
ns
Clock high pulse width
tCHW
2.5
-
3
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
3
-
3
-
3
-
3
-
ns
1
Access time from
clock
CAS Latency = 3
tAC3
-
5.4
-
6
6
6
-
8
ns
2
CAS Latency = 2
tAC2
-
6
-
6
6
-
6
-
8
ns
Data-out hold time
tOH
2.7
-
3
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
2
-
2
-
2
-
3
-
ns
1
Data-Input hold time
tDH
0.8
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
2
-
2
-
2
-
3
-
ns
1
Address hold time
tAH
0.8
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
2
-
2
-
2
-
3
-
ns
1
CKE hold time
tCKH
0.8
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
2
-
2
-
2
-
3
-
ns
1
Command hold time
tCH
0.8
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1
-
1
-
ns
CLK to data output
in high Z-time
CAS Latency = 3
tOHZ3
2.7
5.4
3
6
3
6
3
6
3
8
ns
CAS Latency = 2
tOHZ2
3
6
3
6
3
6
3
6
3
8
ns
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