參數(shù)資料
型號: HY57V653220BTC-7
廠商: HYNIX SEMICONDUCTOR INC
元件分類: DRAM
英文描述: 4 Banks x 512K x 32Bit Synchronous DRAM
中文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86
文件頁數(shù): 8/12頁
文件大小: 154K
代理商: HY57V653220BTC-7
Rev.1.6/Dec. 01
8
HY57V653220B
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-5
-55
-6
-7
-8
-10P
-10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS cycle time
Operation
tRC
55
-
55
-
60
-
63
-
68
-
70
-
70
-
ns
Auto Refresh
tRRC
55
-
55
-
60
-
63
-
68
-
70
-
70
-
ns
RAS to CAS delay
tRCD
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS active time
tRAS
40
100K
38.5
100K
42
100K
42
100K
48
100K
50
100K
50
100K
ns
RAS precharge time
tRP
15
-
16.5
-
18
-
20
-
20
-
20
-
20
-
ns
RAS to RAS bank active delay
tRRD
10
-
11
-
12
-
14
-
16
-
20
-
20
-
ns
CAS to CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-in to active command
tDAL
4
-
4
-
4
-
4
-
4
-
4
-
4
-
CLK
DQM to data-out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to data-in mask
tDQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to new command
tMRD
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to
data output Hi-Z
CAS Latency =
3
tPROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency =
2
tPROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
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