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參數(shù)資料
| 型號： | HY57V653220BTC-6 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 512K x 32Bit Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HY57V653220BTC-6 |
Rev.1.6/Dec. 01
11
HY57V653220B
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
′
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-READ-Single-WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge power
down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V653220BTC-7 | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V653220BTC-8 | 4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V658010 | 8Mx8 bit Synchronous DRAM Series |
| HY57V648010 | 8Mx8 bit Synchronous DRAM Series |
| HY57V648011 | 8Mx8 bit Synchronous DRAM Series |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V653220BTC-6I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SDRAM |
| HY57V653220BTC-7 | 制造商:Hyundai 功能描述:SDRAM, 2M x 32, 86 Pin, Plastic, TSSOP |
| HY57V653220BTC-7I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x32 SDRAM |
| HY57V653220BTC-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 512K x 32Bit Synchronous DRAM |
| HY57V653220BTC-I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2Mx32|3.3V|4K|5/55/6|SDR SDRAM - 64M |
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