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參數(shù)資料
| 型號(hào)： | HY57V643220DT-5 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 4Banks x 512K x 32bits Synchronous DRAM |
| 中文描述： | 2M X 32 SYNCHRONOUS DRAM, 4.5 ns, PDSO86 |
| 封裝： | 0.400 X 0.875 INCH, 0.50 MM PITCH, TSOP2-86 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 227K |
| 代理商： | HY57V643220DT-5 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
Rev. 0.3 / Sep. 2004
6
HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1
0
BA0
0
A11
0
A10
0
A9
A8
0
A7
0
A6
A5
A4
A3
BT
A2
A1
A0
OP Code
CAS Latency
Burst Length
OP Code
A9
0
1
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
Burst Type
A3
0
1
Burst Type
Sequential
Interleave
Burst Length
A2
A1
A0
Burst Length
A3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
A3=1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V643220DT-55 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-6 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-7 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-45 | 4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-5 | 4Banks x 512K x 32bits Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V643220DT-55 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-6 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DT-7 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-45 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
| HY57V643220DTP-5 | 制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:4Banks x 512K x 32bits Synchronous DRAM |
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